Principal Signoff CAD Engineer

Job Title

Principal Signoff CAD Engineer

Role Summary

Join Microsoft SCHIE (Silicon, Cloud Hardware, and Infrastructure Engineering) to define and own signoff CAD strategy and flow architecture for next-generation silicon programs. The role focuses on ensuring production-quality convergence across parasitic extraction, static timing analysis, power integrity, and physical verification.

This is a hands-on principal engineering role that combines technical leadership, vendor engagement, and flow architecture to deliver high-quality silicon at scale.

Experience Level

Senior / Principal level. Typical background: ~8+ years of signoff CAD or equivalent engineering experience; preferred 10+ years of hands-on signoff work at advanced nodes (5nm and below).

Responsibilities

Primary responsibilities include:

• Own and architect end-to-end signoff CAD flow across parasitic extraction, STA, power integrity/IR-drop, and physical verification.
• Establish and enforce signoff methodologies, quality metrics, and validation frameworks to minimize silicon escapes and re-spins.
• Drive technical engagement with EDA vendors to evaluate, qualify, and deploy tool versions and resolve critical tool issues.
• Collaborate with physical design and RTL teams to achieve timing, power, and physical verification closure across concurrent programs.
• Lead and grow the signoff engineering capability by defining standards, conducting reviews, and setting technical direction for signoff decisions.
• Support multiple concurrent tapeouts and ensure production-quality convergence at advanced process nodes.

Requirements

Must-have technical skills and other requirements:

• Deep hands-on experience with signoff tool ecosystems (examples: Synopsys StarRC / PrimeTime / Fusion Compiler; Cadence Pegasus / Tempus / Innovus) and ability to operate across Synopsys and Cadence toolchains.
• Proven delivery of production signoff flows (parasitic extraction, STA, power integrity, physical verification) for advanced-node silicon.
• Strong scripting and automation skills (TCL, Python) for flow development and infrastructure.
• Experience leading signoff convergence across multiple tapeouts with strong quality outcomes.
• Experience with vendor qualification, troubleshooting, and influencing vendor roadmaps for signoff tools.
• Familiarity with cloud-based EDA compute environments and CI/CD practices for CAD flow development.
• Ability to meet Microsoft security screening and provide required documentation for export-controlled information (see Education Requirements for details).

Nice-to-have:

• Track record of establishing reusable, scalable flow architectures across multiple silicon programs.
• Prior experience with Redhawk-SC, Voltus, or equivalent power-IR analysis tools.

Education Requirements

Candidates typically hold a degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. The posting allows: Doctorate + 3+ years, Master’s + 6+ years, Bachelor’s + 8+ years, or equivalent practical experience. Preferred profiles cite Bachelor’s +10+ years or Master’s +8+ years for signoff CAD roles. As a condition of employment for access to export-controlled information, candidates must be able to provide proof of citizenship or lawful residency (passport or other accepted documentation) for eligibility verification.

About the Company

Company: Microsoft

Headquarters: Redmond, Washington, United States

Microsoft is a global technology company that develops and sells software, services, devices, and solutions. Known for its Windows operating system, Office suite, and Azure cloud platform, Microsoft aims to empower individuals and organizations around the world to achieve more. The company fosters a culture of innovation and inclusion, focusing on delivering trusted experiences to customers and partners globally.