Principal Signoff CAD Engineer

Job Title

Principal Signoff CAD Engineer

Role Summary

Principal individual contributor responsible for architecting and owning the end-to-end silicon signoff CAD strategy for Microsoft’s next-generation silicon programs. The role is part of Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) and the Methodology, Infrastructure, Silicon Engineering, and Labs (MILE) team, focused on signoff across extraction, timing, power integrity, and physical verification for advanced-node designs.

Experience Level

Senior — Principal-level technical IC engineering role. Typical candidates have many years of signoff CAD experience (see Education Requirements for formal degree/years combinations and equivalency).

Responsibilities

Own and drive signoff CAD strategy, quality, and tool adoption across multiple silicon programs.

• Architect and maintain end-to-end signoff flows for parasitic extraction, static timing analysis, power integrity/IR-drop, and physical verification.
• Establish signoff best practices, quality metrics, and validation frameworks to prevent escapes and reduce re-spins.
• Lead technical engagements with EDA vendors to qualify and deploy tool versions and resolve critical tool issues.
• Collaborate with physical implementation and RTL teams to drive timing, power, and verification closure across concurrent tapeouts.
• Grow and mentor the signoff engineering team; set technical standards and conduct design reviews.

Requirements

Key technical skills, security, and operational requirements. Degree and formal years-of-experience combinations are summarized in Education Requirements below.

• Hands-on experience with signoff tool ecosystem: Synopsys StarRC and/or Cadence Pegasus (extraction); Synopsys PrimeTime and/or Cadence Tempus (STA); Synopsys Redhawk‑SC and/or Cadence Voltus (power/IR); Synopsys Fusion Compiler and/or Cadence Innovus (implementation/physical verification).
• Proven experience delivering production-quality signoff convergence for advanced process nodes (experience with 5nm and below is strongly preferred).
• Strong scripting and automation skills (TCL and Python) for production flows and infrastructure automation.
• Experience qualifying and evaluating competing EDA solutions and influencing vendor roadmaps.
• Track record of leading signoff on multiple concurrent tapeouts with high silicon quality and low escape rates.
• Familiarity with cloud-based EDA compute environments and CI/CD practices for CAD flow development (preferred).
• Ability to work with geographically distributed teams and collaborate across implementation, RTL, and manufacturing stakeholders.
• Travel: less than 25%.
• Must be able to meet Microsoft security screening requirements, including the Microsoft Cloud Background Check; role requires eligibility to access export-controlled information and verification of citizenship or residency documentation.

Education Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related technical field plus 3+ years technical engineering experience; OR Master’s degree in those fields plus 6+ years; OR Bachelor’s degree in those fields plus 8+ years; OR equivalent practical experience. Preferred qualification examples cited: Bachelor’s +10+ years or Master’s +8+ years in silicon signoff CAD engineering. Fields explicitly referenced: Electrical Engineering, Computer Engineering, Computer Science, or related technical fields. "Equivalent experience" is accepted.

About the Company

Company: Microsoft

Headquarters: Redmond, Washington, United States

Microsoft is a global technology company that develops and sells software, services, devices, and solutions. Known for its Windows operating system, Office suite, and Azure cloud platform, Microsoft aims to empower individuals and organizations around the world to achieve more. The company fosters a culture of innovation and inclusion, focusing on delivering trusted experiences to customers and partners globally.