Principal Signal/Power Integrity Engineer

Job Title

Principal Signal/Power Integrity Engineer

Role Summary

Senior engineer in the Signal Integrity Engineering (SIE) group responsible for power delivery network (PDN) and high-speed signal integrity at board and package levels. The role defines and validates electrical solutions that meet performance and cost targets for Marvell switch products and collaborates across layout, IP, and system teams.

Experience Level

Senior — typically 10–15 years of related industry experience.

Responsibilities

Key day-to-day responsibilities include simulation, design validation, and cross-functional collaboration to deliver PDN and SI solutions.

• Develop power-delivery solutions for devices at package and system levels.
• Evaluate designs to ensure they meet electrical performance requirements and constraints.
• Collaborate with layout engineers and IP teams to optimize PDN and signal paths.
• Perform simulations and tool evaluations; develop flows and scripting to improve efficiency.
• Create and validate signal integrity solutions for high-speed device interfaces using electromagnetic simulation tools.

Requirements

Must-have technical skills and experience, followed by advantageous skills.

• Must-have: Deep power integrity expertise including inductance and capacitance behavior and PDN design, modeling, and analysis (experience with tools such as PowerSI and SIwave).
• Must-have: Strong understanding of package and board implementation limitations and constraints.
• Must-have: Deep knowledge of signal integrity concepts and high-speed interface behavior.
• Must-have: Proven ability to collaborate across multiple geographies and strong communication, presentation, and documentation skills.
• Nice-to-have / Advantage: Experience with 3D electromagnetic extraction tools (e.g., Ansys HFSS) and 2.5D/3D package development.
• Nice-to-have / Advantage: Hands-on power-supply measurement experience and familiarity with packaging technologies, materials, substrate design rules, and assembly processes.
• Nice-to-have / Advantage: Experience with high-speed interfaces such as DDR4, PCIe Gen3/4, and multi-rate Ethernet (10G/25G/50G/100G/200Gbps).
• Nice-to-have / Advantage: Familiarity with Cadence Allegro schematics and layout tools.
• Must-have: Strong analysis and problem-solving skills; detail-oriented and fact-based decision making.

Education Requirements

Bachelor of Science (BSc) in Electrical Engineering is specified. The posting references senior-level experience (approximately 10–15 years) alongside the BSc requirement.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.