Principal Signal Integrity Engineer, Satellites (Starlink)

Job Title

Principal Signal Integrity Engineer, Satellites (Starlink)

Role Summary

Lead signal-integrity engineering for Starlink satellite payload hardware across design, verification, qualification, and production phases. Work at the intersection of electrical, mechanical, thermal, packaging, and RF engineering to define channels, stack-ups, and SI verification approaches for high-speed SERDES and memory interfaces.

Contribute processes, tools, and lab methods for SI signoff and mentor engineers across the Starlink program.

Experience Level

Senior / Principal level. Posting specifies 5+ years of industry or research experience in high-speed digital design and use of 3D EM and channel simulation tools.

Responsibilities

Primary responsibilities include SI architecture, simulation, verification, and troubleshooting for satellite payload hardware.

• Specify, design, simulate, verify, qualify, and define production screens for SI of wireline and electro-optical communication systems (e.g., 10–112+ Gbps SERDES, DSPs, retimers, optoelectronics).
• Specify and validate high-speed/high-bandwidth memory interfaces (DDR4, LPDDR5, GDDR/GPDDR, QSPI NOR, eMMC, etc.).
• Define PCB material and channel subcomponent specifications and derive top-level channel requirements.
• Design and optimize transition structures across the entire channel (die bump to die bump) including package and PCB transitions.
• Lead root-cause analysis and fixes for issues from PCB manufacturing, PCBA test, or satellite integration.
• Define SI best practices, simulation workflows, test methodologies, signoff criteria, and lab-equipment needs for payloads.
• Collaborate closely with RF, antenna, ASIC, packaging, mechanical, thermal, software, supply chain, and production engineering teams.

Requirements

Expectations are separated into must-have core requirements and preferred skills.

Must-have

• 5+ years industry or research experience in high-speed digital design and hardware development.
• 5+ years using 3D EM solvers and high-speed channel simulation tools (examples: CST, HFSS, ADS).
• Demonstrated experience specifying, analyzing, and debugging high-speed wireline channels and memory interfaces.
• Proven ability to troubleshoot SI issues across package, PCB, and system integration phases.
• Willingness to work extended hours or weekends as needed and travel occasionally.
• Must meet U.S. export-control eligibility (U.S. citizen, U.S. national, U.S. lawful permanent resident, refugee, asylee, or otherwise eligible for required Department of State authorizations).

Nice-to-have / Preferred

• Experience architecting and debugging DSP-based SERDES at advanced data rates (e.g., 56–224 Gbps) across package and PCB.
• Experience with low-loss laminates, high-volume PCB manufacturing, and high-speed connectors.
• Experience debugging EMI/EMC de-sense and related mitigation strategies.
• Strong programming skills (Python, C/C++) and familiarity with automation for SI workflows.
• Demonstrated effectiveness in cross-functional roles coordinating ASIC, package, PCB, and mechanical optimizations.

Education Requirements

Required: Bachelor's degree in Electrical Engineering, Computer Engineering, or Physics. Preferred: Master's degree or PhD in Electrical or Computer Engineering with emphasis in electromagnetic theory, transmission-line theory, or wireline transceivers. The posting also notes internships, co-ops, and research/lab work count toward experience.

About the Company

Company: SpaceX

Headquarters: Hawthorne, California, United States

SpaceX is focused on developing space technologies to enable human exploration of Mars and beyond. The company is known for its advancements in rocketry and its Starlink satellite constellation, which delivers high-speed internet globally.