Principal SI/PI Engineer

Job Title

Principal SI/PI Engineer

Role Summary

Lead signal- and power-integrity engineering for high-speed SerDes interfaces across silicon, package, interposer, PCB, connectors, and compliance fixtures. Act as a technical owner for SI/PI signoff methodology, channel modeling, lab correlation, and cross-functional problem solving.

Work on SerDes links such as PCIe (Gen6/7/8), E224G, E448G and CXL, collaborating with PHY, package, board, validation and product teams to ensure reliable, high-performance system integration. Accommodation contact: hr-help-canada@synopsys.com.

Experience Level

Senior - 12+ years of relevant experience in high-speed SI/PI for SerDes links (silicon + package + board).

Responsibilities

Primary responsibilities include end-to-end SIPI ownership, modeling, signoff, correlation, and technical leadership.

• Lead SIPI for SerDes interfaces across die, package, interposer, PCB, connectors, and fixtures.
• Develop and validate channel models; perform time- and frequency-domain analysis (S-parameters, TDR, VNA, crosstalk, jitter/noise budgeting, eye-margin and link-margin simulations).
• Own SI signoff methodology: model extraction/quality checks, de-embedding, and ensuring model bandwidth for target data rates.
• Plan and execute lab correlation and compliance testing; design or advise on fixtures and de-embedding/calibration approaches.
• Partner with circuit/PHY, package, board, and product teams to diagnose bring-up issues and recommend quantified design changes.
• Document reusable guidelines, define SIPI flows and checklists, lead technical reviews, and mentor engineers.
• Provide program-level technical leadership: set priorities, identify reuse opportunities, and influence architecture decisions affecting SI/PI.

Requirements

Must-have technical skills, tools familiarity, and professional experience.

• Must-have: 12+ years of hands-on experience in high-speed SI/PI for SerDes links in silicon, package, and board domains, preferably in interface IP or high-volume products.
• Must-have: Strong fundamentals in electromagnetics, transmission-line theory, passive/active modeling, statistical link analysis, and translating system requirements into measurable signoff criteria.
• Must-have: Expertise in high-speed link concepts (insertion/return loss, impedance control, mode conversion, NEXT/FEXT, jitter/noise sources, equalization, BER).
• Must-have: Experience with modeling, simulation and EM tools such as HSPICE, Keysight ADS/SystemVue, Ansys HFSS/SIwave/AEDT, Cadence Sigrity, and familiarity with model formats (Touchstone, IBIS-AMI, SPICE, EM-based RLGC).
• Must-have: Practical lab and correlation experience (TDR, VNA, eye/jitter measurements, de-embedding/fixture calibration) and working with validation/compliance teams.
• Must-have: Scripting/automation skills for flow enablement (Python preferred; MATLAB/TCL a plus) and strong documentation practices for reproducibility.
• Must-have: Demonstrated technical leadership: mentoring, leading design reviews, and influencing cross-functional decisions.
• Nice-to-have: Prior experience with PCIe Gen6/7/8, E224G/E448G, CXL over PCIe, or similar high-data-rate SerDes links in advanced packaging environments.

Education Requirements

Bachelor's degree in Electrical/Electronic Engineering or related field required; M.S. or Ph.D. preferred. Equivalent practical experience may be acceptable where demonstrated by relevant SI/PI engineering and technical leadership.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.