Principal SerDes Validation Engineer

Job Title

Principal SerDes Validation Engineer

Role Summary

Lead post-silicon validation and electrical characterization for high-speed SerDes PHYs (PCIe, Ethernet and storage interfaces). Work in the post-silicon validation group to design test platforms, develop automated test suites, perform lab bring-up, and drive silicon characterization across process, voltage and temperature to determine production readiness.

Experience Level

Senior-level. Typically expected to have extensive industry experience; the company assesses candidates during interview and assigns level/offer accordingly.

Responsibilities

Primary responsibilities include development and execution of PHY validation plans, lab bring-up, signal analysis and cross-team debugging.

• Define, document, execute and report PHY validation and test plans for PCIe, Ethernet and storage interfaces.
• Perform lab-based silicon bring-up and unit tests focused on physical and PCS layer hardware and firmware; extend testing to protocol-layer behavior where required.
• Measure and analyze high-speed signals (eye diagrams, jitter, BER) using oscilloscopes, BERTs, network analyzers and protocol analyzers.
• Debug failing tests using diagnostics, software tools, hardware analyzers and collaboration with firmware/software teams.
• Develop automated test frameworks and measurement scripts to characterize analog interfaces across PVT corners.
• Lead technical discussions with cross-functional teams, external vendors and customers to resolve silicon issues and field failures.
• Document test results, provide actionable reports, and recommend design or process changes to improve yield and performance.

Requirements

Must-have technical skills, tools and experiences; listed concisely.

• Strong practical understanding of high-speed SerDes and equalization techniques.
• 5+ years experience with high-speed I/O testing, debugging and validation.
• 5+ years direct experience in SerDes characterization or SerDes design.
• Experience using test equipment for SerDes characterization: oscilloscopes, BERTs, network analyzers, protocol analyzers.
• Deep understanding of high-speed electrical signaling principles, differential signaling and mixed-signal behavior.
• Experience developing automation using Python and familiarity with mathematical tools such as MATLAB.
• Experience with SerDes modeling techniques and signal integrity analysis.
• Strong troubleshooting, critical thinking, and ownership of validation results; excellent verbal and written communication skills.
• Ability to work with customers and vendors to reproduce and debug field issues.
• Must be eligible to access export-controlled technology where required (export license review may apply for non-U.S. citizens).
• Nice-to-have: detailed knowledge of NRZ and PAM4 signaling and relevant Ethernet standards (10GbE, 100GbE, 400GbE) and experience with PCIe protocol-layer validation.

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering, or a related field with ~10+ years of relevant professional experience; OR a Master's degree or PhD in Computer Science, Electrical Engineering, or related field with approximately 3–5 years of experience. (The posting indicates offers and level may vary by qualifications.)

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.