Principal RTL Design Engineer

Job Title

Principal RTL Design Engineer

Role Summary

Senior individual contributor responsible for owning the microarchitecture and RTL for a major block or subsystem of a high-performance AI accelerator (RDU) from specification through RTL, quality closure, and tape-out. Work spans datapath, on-chip network, and memory subsystems and includes PPA trade-offs and timing closure.

Base pay range: $180,000—$255,000 USD.

Experience Level

Senior — requires 7+ years of industry experience in ASIC RTL design.

Responsibilities

Key responsibilities include:

• Own microarchitecture and synthesizable SystemVerilog RTL for a major block or subsystem from spec through tape-out.
• Write, integrate, and debug RTL and support full-chip implementation and production lifecycle.
• Drive power, performance, and area (PPA) trade-offs to meet aggressive frequency targets via pipelining, retiming, and restructuring.
• Drive timing closure and design quality: synthesis, STA, critical-path optimization, lint, CDC, LEC, and SVA.
• Partner with verification, physical design, architects, and software teams to define verification intent and support debug.
• Introduce AI/automation and new EDA tool methodologies into the design flow.
• Provide technical leadership in design reviews and mentor other design engineers.

Requirements

Must-have technical skills and experience:

• 7+ years industry ASIC RTL design experience focused on high-performance designs.
• Mastery of synthesizable SystemVerilog, including SystemVerilog Assertions (SVA).
• High-frequency design experience: datapath pipelining, retiming, and critical-path restructuring.
• Strong foundation in computer architecture and digital logic: arbitration, flow control, CDC, memory structures.
• Proven ownership of a complex block or subsystem through production ASIC tape-out.
• Experience converging PPA against physical constraints (floorplan, congestion, timing feedback).
• Hands-on with synthesis, static timing analysis (STA), lint, CDC, and LEC flows.
• Technical leadership and mentoring ability; ability to set direction in design reviews.
• Scripting in Python for design and flow automation.

Nice-to-have:

• Depth in a specific domain: compute/dataflow datapath, on-chip network/interconnect, or memory subsystem.
• Experience with AXI, PCIe, Ethernet, HBM or DDR, chiplet/multi-die design, or ML acceleration/dataflow architectures.
• Formal property checking, performance modeling, and advanced-node (TSMC) experience.
• Familiarity using AI tools to assist RTL design and flow development.

Education Requirements

Required: B.S. in Electrical Engineering, Computer Engineering, or Computer Science. Preferred: M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science.

About the Company

Company: SambaNova Systems

Headquarters: Palo Alto, CA, United States

Provider of a full‑stack generative AI platform that integrates custom AI accelerator hardware and software. SambaNova delivers the SambaNova Suite and SN40L chip to enable high-performance, on‑premises and cloud deployments for enterprise and government AI workloads.