Principal Research Scientist

Job Title

Principal Research Scientist

Role Summary

Principal individual contributor and technical leader responsible for research and development of next-generation wafer-level interconnects (BEOL), wafer-level packaging (WLP), and heterogeneous integration technologies. Lead proposal development and funded research programs, guide small R&D teams, and transition research concepts into manufacturable solutions that enable new product capabilities.

Experience Level

Senior / Professional. Requires extensive industry experience: typically 10+ years of hands-on semiconductor R&D and 5+ years as a Principal Investigator or technical lead on advanced R&D programs.

Responsibilities

Deliver research, technical leadership, and program execution for wafer and packaging integration technologies.

• Drive research and development of wafer-level interconnects, BEOL processes, WLP, and heterogeneous integration approaches.
• Author and influence technology roadmaps aligned to product and innovation strategies.
• Lead proposal development, capture, and execution of funded programs as Principal Investigator.
• Provide technical project leadership: planning, risk management, and milestone delivery.
• Perform hands-on process ideation, pathfinding, troubleshooting, and execution in cleanroom environments.
• Collaborate with and direct technicians, junior engineers, and process engineers to deliver results.
• Communicate technical status and recommendations to senior leadership, customers, and external stakeholders.
• Generate intellectual property (patents, disclosures) and mentor junior engineers and researchers.

Requirements

Must-have technical skills, experience, and employment constraints. Preferred items listed where noted.

• Must have: 10+ years of hands-on semiconductor R&D experience in cleanroom fabrication environments.
• Must have: 5+ years serving as a Principal Investigator, technical lead, or equivalent leader for advanced R&D programs.
• Must have: Demonstrated expertise in BEOL processing and/or wafer-level packaging (WLP) technologies, including metallization and dielectric integration.
• Must have: Hands-on experience with advanced metallization, dielectric integration, and interconnect process development.
• Must have: Experience with GaAs and/or GaN device fabrication, process integration, and characterization.
• Must have: Working knowledge of device and mask layout design for analog and RF applications; strong written and verbal communication and proposal development skills.
• Must have: Proven ability to lead and guide small, multidisciplinary R&D teams and deliver milestones.
• Must have: This role requires work on U.S. Government contracts; applicants must be a U.S. Person. This position is not eligible for company visa sponsorship.
• Nice to have: Experience with government-sponsored R&D (e.g., DARPA, AFRL), advanced packaging/3D heterogeneous integration, lithography, etch, CMP, SEM/FIB, bonding (Cu-Cu hybrid), wafer thinning, TSVs, RF characterization (S-parameters, load-pull), data analytics/visualization tools, and device reliability/failure analysis.

Education Requirements

Ph.D. in Materials Science, Electrical Engineering, Mechanical Engineering, Chemical Engineering, Physics, or a related technical field.

About the Company

Company: Qorvo

Headquarters: Greensboro, NC, US

Qorvo supplies innovative semiconductor solutions that enhance connectivity and power for a variety of applications, including consumer electronics, automotive, and healthcare. With a focus on RF and power solutions, Qorvo combines technology leadership and global manufacturing to address complex challenges in fast-growing industries. Their commitment to excellence and innovation drives them to shape the future of wireless communications.