Principal R&D Engineer — Enterprise SerDes Physical Implementation
SynopsysJob Title
Principal R&D Engineer — Enterprise SerDes Physical Implementation
Role Summary
Lead physical implementation of high-speed SerDes IP from RTL to GDSII, driving timing closure, signoff, and chip-level integration for mixed-signal IPs on advanced process nodes.
Work with a small engineering team, front-end, analog and CAD groups to define floorplanning, constraints, and automated flows for 56G/112G/224G PAM4/6 SerDes platforms.
Experience Level
Senior — typically MSEE with 10+ years or BSEE with 12+ years of relevant digital/physical design experience (see Education Requirements).
Responsibilities
Accountable for implementation, signoff, team leadership, and automation for high-speed SerDes IP tapeouts.
- Drive physical implementation from RTL to GDSII, including timing closure and physical signoff.
- Lead a small implementation team; set technical direction and remove tapeout blockers.
- Develop timing constraints and floorplanning to meet power, area, and performance targets on TSMC 16nm and below.
- Resolve analog/digital interface issues in collaboration with front-end and analog teams.
- Automate implementation flows using Perl, Tcl, and Python across multiple process technologies.
- Own chip-level integration and signoff for mixed-signal IPs prior to tapeout.
Requirements
Must-have technical skills and experience required to perform the role.
- Proven track record leading physical implementation through multiple tapeouts.
- Deep knowledge of the full design cycle from RTL to GDSII, including chip-level integration.
- Practical experience with TSMC 16nm or below and low-power implementation techniques.
- Strong scripting and CAD automation skills (Perl, Tcl, Python).
- Solid understanding of digital and mixed-signal verification flows and SoC integration.
- Ability to diagnose timing report bottlenecks and propose fixes that balance area and power.
- Willingness to travel internationally as required.
- Nice-to-have: experience with PAM4/6 SerDes platforms and high data-rate (56G/112G/224G) designs.
Education Requirements
MSEE with 10+ years or BSEE with 12+ years in digital or physical design (Electrical Engineering). (These degree-and-experience combinations are stated as the hiring guideline.)
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
