Principal Product Engineer - Memory IP

Job Title

Principal Product Engineer - Memory IP

Role Summary

The Principal Product Engineer will support integration, verification, and customer adoption of memory subsystem IP (controller + PHY). The role works with pre-silicon and post-silicon activities, customer integrations, internal QA, and product documentation to ensure successful SOC memory subsystem implementations.

Work involves technical customer support, root-cause analysis, system-level reviews, and application of AI tools to improve productivity and analytics.

Experience Level

Senior — principal level. Typical experience guidance from the posting: 7+ years with a BS or 5+ years with an MS, or equivalent practical experience.

Responsibilities

Primary duties include technical integration support, verification, and customer-facing engineering assistance.

• Support pre-silicon integration, usage, and implementation of memory subsystem products (controller + PHY).
• Conduct internal system integration and QA testing of memory subsystems.
• Analyze and resolve complex subsystem application or implementation issues; provide professional guidance to customers.
• Participate in memory PHY and controller SOC integration and implementation reviews.
• Assist customers with RTL and gate-level simulations to verify functionality.
• Support timing closure and other aspects of physical integration for customer designs.
• Contribute to product documentation, customer checklists, and integration guides.
• Support post-silicon bring-up and production test activities as needed.
• Provide prompt, technically accurate responses to customer questions and support requests.
• Leverage AI-powered tools and analytics to improve productivity, decision making, and deliverable quality.

Requirements

Key technical requirements and preferred skills.

Must-have:

• Experience with memory interfaces/IP such as DDR5/4/3, LPDDR5/4/3, HBM3, GDDR6, or similar.
• Verilog RTL design and gate-level verification experience.
• Synthesis and static timing analysis (STA) experience; physical implementation/verification is a plus.
• Familiarity with industry-standard DFT flows and test methodologies.
• Familiarity with package and board design; ability to read schematics and participate in SI/PI reviews.
• Experience supporting customer integration reviews, implementation reviews, and system-level debugging.

Nice-to-have:

• Experience with Memory PHY designs and DSP-based architectures.
• Experience with embedded microcontroller firmware.
• Scripting skills and experience applying AI solutions to engineering workflows.

Education Requirements

B.S. in Electrical or Computer Engineering (or similar) with 7+ years of experience, or M.S. in Electrical or Computer Engineering (or similar) with 5+ years of experience. Equivalent practical experience acceptable.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.