Principal Product Engineer – High-Speed IP UCIE

Job Title

Principal Product Engineer – High-Speed IP UCIE

Role Summary

Technical product owner and senior engineering lead on a high-speed IP team responsible for post-sales support, integration, and product readiness for die-to-die and PHY/controller subsystems (UCIe, PCIe, USB, DPHY, Ethernet, DDR, LPDDR, GDDR, HBM).

The role interfaces directly with customers and Cadence R&D to resolve complex integration and silicon issues and to drive adoption and product improvements.

Experience Level

Senior - typically 7+ years of relevant engineering experience.

Responsibilities

Primary responsibilities across pre-sales, pre-silicon, and post-silicon phases.

• Serve as primary product engineering owner for UCIe die-to-die subsystems at the customer level.
• Lead customer technical engagements, design reviews, and deployment strategy discussions.
• Drive resolution of complex subsystem integration and implementation issues.
• Lead SoC integration reviews covering PHY and controller subsystems.
• Provide technical leadership for RTL, gate-level simulations, and timing-closure strategies.
• Define and improve integration methodologies, checklists, and customer collateral.
• Lead post-silicon bring-up and debug activities to ensure successful customer deployment.
• Collaborate with R&D, validation, and applications teams to deliver product readiness.
• Mentor junior engineers and provide technical guidance across projects and teams.
• Leverage AI tools to improve debug efficiency, data analysis, and decision-making.

Requirements

Core technical and professional requirements. Education and degree equivalencies are listed in the Education Requirements section below.

• Must-have: Proven experience with high-speed interface IP and subsystem integration (UCIe, PCIe, DDR-family, Ethernet, USB, etc.).
• Must-have: Deep understanding of RTL design, gate-level verification, and simulation methodologies.
• Must-have: Experience with synthesis, static timing analysis (STA), and timing closure strategies; backend knowledge is a plus.
• Must-have: Familiarity with DFT methodologies, test flows, and system validation approaches.
• Must-have: Demonstrated ability to lead cross-functional technical efforts and represent the organization in customer-facing technical roles.
• Must-have: Strong communication skills, ownership mindset, and ability to manage multiple priorities and escalations.
• Nice-to-have: Experience with memory and other high-speed interfaces (DDR, LPDDR, GDDR, HBM) and analog/mixed-signal design practices.
• Nice-to-have: Hands-on experience in silicon debug, post-silicon bring-up, and customer deployment environments.
• Nice-to-have: Familiarity with AI-assisted workflows and data-driven debug techniques.

Education Requirements

Bachelor's in Electrical Engineering, Computer Engineering, or a related field (typically paired with 7+ years relevant experience); or Master's with ~5+ years; or PhD with relevant experience. Equivalent practical experience may be acceptable.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.