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Principal Product Engineer – High-Speed IP Memory

Cadence Design Systems
September 14, 2026
Full-time
On-site
Seoul, KR
Semiconductor IP Jobs, Level - Senior

Job Title

Principal Product Engineer – High-Speed IP Memory

Role Summary

Lead product engineering for memory and high-speed interface IP across the full product lifecycle, focusing on customer integration, pre- and post-silicon support, and technical escalations. Part of a global IP team supporting DDR, LPDDR, GDDR, HBM and other high-speed PHYs and controllers.

Responsible for technical leadership, driving cross-functional execution, and ensuring successful customer adoption.

Experience Level

Senior - principal-level role. See Education Requirements for degree-specific experience guidance.

Responsibilities

Primary duties include customer-facing engineering, integration, and post-silicon support.

  • Act as primary product engineering owner for memory subsystems (DDR, LPDDR, GDDR, HBM) at the customer level.
  • Lead customer engagements, technical discussions, design reviews, and deployment strategy.
  • Drive resolution of complex subsystem integration and implementation issues.
  • Lead SoC integration reviews covering PHY and controller subsystems.
  • Provide technical leadership for RTL, gate-level simulation, and timing-closure strategies.
  • Define and improve integration methodologies, checklists, and customer collateral.
  • Lead post-silicon bring-up, debug activities, and customer deployment support.
  • Collaborate with R&D, validation, and applications teams to deliver product readiness.
  • Mentor junior engineers and provide technical guidance across projects.
  • Leverage AI tools to improve debug efficiency, data analysis, and decision-making.

Requirements

Required technical skills and professional behaviors for the role.

  • Strong experience with high-speed interface IP and memory subsystem integration.
  • Deep understanding of RTL design, gate-level verification, and simulation methodologies.
  • Experience with synthesis, static timing analysis (STA), and timing closure; backend knowledge is a plus.
  • Familiarity with DFT methodologies, test flows, and system validation approaches.
  • Proven ability to troubleshoot and drive complex technical issues to root cause and resolution.
  • Experience leading cross-functional technical efforts and managing multiple priorities and escalations.
  • Strong customer-facing skills and experience representing engineering teams with customers.
  • Excellent verbal and written communication; ability to influence internal and external stakeholders.
  • Ownership mindset with ability to drive deliverables independently and mentor others.

Education Requirements

Bachelor's in Electrical Engineering, Computer Engineering, or related field with 7+ years of relevant experience; or Master's with 5+ years; or PhD with relevant experience. Equivalent practical experience may be considered.


About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.

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Date Posted: 2026-09-14