Principal Product Engineer

Job Title

Principal Product Engineer

Role Summary

Senior technical authority within Cadence's Digital and Signoff Group (DSG) responsible for driving product and methodology improvements across the digital implementation portfolio (Innovus, Tempus, Genus). The role interfaces directly with strategic customers and R&D architects to resolve high‑priority technical challenges and shape the roadmap for advanced process nodes.

Experience Level

Senior — typically 6–8 years of hands-on experience in ASIC physical design and/or EDA product engineering with a track record of shipping designs or product improvements.

Responsibilities

Accountable for high‑impact technical work spanning customer engagement, benchmark development, and product validation. Key responsibilities include:

• Own and resolve complex customer escalations as the senior technical point of contact for strategic accounts.
• Lead development and execution of advanced design benchmarks for 7nm, 5nm, 3nm and next‑generation nodes focused on PPA and runtime.
• Partner with R&D architects to identify product gaps, propose algorithmic improvements, and validate feature releases.
• Define reference methodologies and best‑practice flows for hierarchical and flat implementation using the Cadence digital toolchain.
• Mentor product engineers and perform technical reviews of code, flows, and implementation results.
• Drive automation and scalable infrastructure using Tcl, Perl, Python, and Shell for regression testing and benchmarking.
• Represent DSG in customer technical reviews, DFM workshops, and industry events; synthesize customer feedback into roadmap recommendations.

Requirements

Concise list of required and preferred technical qualifications.

• Must-have: 6–8 years of deep, hands-on experience in ASIC physical design and/or EDA product engineering with demonstrated delivery and problem resolution.
• Must-have: Expert-level understanding of the RTL-to-GDSII flow: synthesis, floorplanning, placement, CTS, routing, static timing analysis, and physical sign-off.
• Must-have: Proven experience with timing closure and PPA optimization at 16nm and below (including 10nm, 7nm, 5nm FinFET).
• Must-have: Proficiency with Cadence Innovus, Tempus, and Genus; familiarity with Pegasus is an asset.
• Must-have: Advanced static timing analysis skills (MMMC, POCV/AOCV, hold optimization, CDC methodology).
• Must-have: Strong scripting and automation skills: advanced Tcl plus Perl, Python, Shell; experience building reusable flow infrastructure.
• Nice-to-have: Experience with Joules, Voltus or integrated Innovus‑Tempus signoff flows.
• Nice-to-have: Knowledge of advanced routing constraints (SADP, EUV rules) or chip design experience in automotive (ISO 26262), AI/ML accelerators, or HPC domains.
• Nice-to-have: Prior R&D engineering experience at an EDA or semiconductor company.

Education Requirements

B.E. or M.S. in Electrical Engineering or a related discipline as stated in the posting.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.