Principal Power Design Engineer

Job Title

Principal Power Design Engineer

Role Summary

Own design, implementation, and validation of power delivery systems for high-performance AI compute hardware. Collaborate with hardware, package, SI/PI, firmware, and systems teams to ensure stable power under dynamic AI workloads.

Hands-on role combining schematic and layout oversight, component selection, and laboratory validation of multi-phase regulators and point-of-load converters.

Experience Level

Senior-level (Principal). The role requires extensive senior experience in high-current power design; no specific years-of-experience were listed.

Responsibilities

Primary responsibilities include design, validation, and cross-team coordination:

• Design schematics for multi-phase buck regulators, point-of-load converters, and power sequencing circuitry.
• Select passives, inductors, power stages, controllers, and supporting components.
• Define placement and routing constraints for board-level PDN, decoupling strategy, and high-current power paths.
• Coordinate with package engineering to ensure clean power handoff at socket/package interfaces.
• Lead lab validation of power subsystems: VRM efficiency, loop stability, DC IR drop, thermal behavior, and transient response.
• Use oscilloscopes, electronic loads, network analyzers, thermal cameras, and related equipment to characterize power under dynamic loads.
• Partner with SI/PI engineers to measure and mitigate power supply noise and power-supply-induced jitter on high-speed lanes.
• Debug power integrity issues across board, package, silicon, firmware, and system-level interactions.
• Develop design guidelines, validation plans, and best practices for power delivery across platforms.

Requirements

Must-have technical skills and experience:

• Extensive experience designing high-current, multi-phase DC-DC regulators for ASICs, GPUs, processors, accelerators, or comparable compute platforms.
• Experience with systems containing 500W+ devices or similar high-current power delivery requirements.
• Deep understanding of board-level PDN implementation, decoupling strategy, power sequencing, transient response, and voltage regulation.
• Hands-on schematic capture and layout oversight experience; familiarity with Cadence Allegro, Concept, or similar tools.
• Strong lab validation skills using electronic loads, oscilloscopes, network analyzers, thermal cameras; experience with loop stability testing.
• Experience characterizing VRM efficiency, bode plots, DC IR drop, ripple, noise, and transient behavior under dynamic workloads.
• Proficiency with SPICE-based time-domain circuit simulation or equivalent power simulation workflows.
• Ability to collaborate with SI/PI, package, hardware, firmware, and systems teams in a fast-moving engineering environment.

Nice-to-have:

• Experience with power delivery for AI accelerators, GPUs, networking ASICs, switch ASICs, or high-performance server platforms.
• Familiarity with power integrity interactions affecting high-speed SerDes, PCIe, Ethernet, CXL, or other sensitive interfaces.
• Experience validating power systems under real workload conditions, including dynamic AI inference or high-utilization compute workloads.
• Exposure to package-level power delivery, socket interfaces, or advanced board/package co-design.
• Experience developing automated lab validation flows using Python or similar scripting languages.

Education Requirements

Not specified.

About the Company

Company: Delos Data

Headquarters: Palo Alto, CA, United States

Stealth-mode Silicon Valley startup building foundational technology to improve performance, scalability, and resiliency of large-scale AI data center clusters. Backed by venture capital and led by experienced founders, the company develops hardware/software solutions and operates across U.S. and Canadian locations.