Principal Post-Silicon Applications Engineer

Job Title

Principal Post-Silicon Applications Engineer

Role Summary

Senior applications engineer responsible for post-silicon bring-up, debugging, and customer support for high-speed SerDes and PCIe 6.0/7.0 silicon. Work spans laboratory measurements, RTL analysis, firmware and system-level interactions, and direct customer engagement.

Member of a multi-site applications team providing technical authority and integration support to enable customer tape-outs and production ramps.

Experience Level

Senior - typically requires 10+ years of hands-on experience in post-silicon validation, applications engineering, or SerDes bring-up.

Responsibilities

The role focuses on diagnosing complex silicon and system issues, leading root-cause analysis, and collaborating with customers and internal design teams to resolve blockers.

• Provide senior-level technical support during silicon bring-up and production, including on-site engagement for critical issues.
• Lead root-cause analysis for signal integrity, protocol compliance, and interoperability across analog, digital, and system layers.
• Use advanced lab instrumentation (high-bandwidth oscilloscopes, spectrum analyzers, BER testers, VNAs, protocol analyzers) to isolate failure mechanisms at 64 GT/s and higher.
• Analyze and simulate Verilog/SystemVerilog RTL and collaborate with digital and firmware teams to resolve implementation issues.
• Drive technical engagements with customer engineering teams and translate findings into actionable recommendations.
• Develop and refine test methodologies, debug procedures, and best practices for SerDes validation and customer deployment.
• Travel approximately twice per year to customer sites or internal labs for critical bring-up support.

Requirements

Key technical qualifications and practical skills required to perform the role.

• Must have: 10+ years of hands-on experience in post-silicon validation, applications engineering, or SerDes bring-up.
• Must have: Extensive expertise with PCIe 6.0 or newer, including PAM4 signaling, FLIT mode operation, link training protocols, and compliance testing at 64 GT/s and above.
• Must have: Proficiency with advanced laboratory equipment for signal integrity and protocol debug (oscilloscopes, spectrum analyzers, BER testers, VNAs, protocol analyzers).
• Must have: Experience analyzing and simulating Verilog/SystemVerilog RTL to diagnose digital issues affecting silicon behavior.
• Must have: Strong practical knowledge of high-speed PCB design, signal integrity principles, power delivery architectures, and system-level integration.
• Nice to have: Prior experience leading customer technical engagements and producing structured debug reports and design guidance.
• Nice to have: Experience with compliance lab workflows and production ramp support.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related technical discipline (as stated in the source). (Education language present in source: Bachelor's, Master's; fields: Electrical Engineering, Electronics Engineering, related disciplines.)

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.