Principal Physical Design/Implementation Engineer

Job Title

Principal Physical Design/Implementation Engineer

Role Summary

Lead physical design and implementation for complex SubSystems within the Custom Compute and Storage (CCS) Business Unit. The role drives RTL-to-GDSII execution, floorplanning, timing closure and production-quality delivery of SubSystem partitions to SOC teams.

Part of the SubSystem Physical Implementation Center of Excellence (CoE); collaborate with RTL, verification, CAD and cross-functional teams and influence methodology and tooling choices.

Experience Level

Senior (Principal). This role expects significant hands-on implementation leadership; see Education Requirements for specific years-of-experience guidance.

Responsibilities

Primary responsibilities include technical leadership, hands-on implementation, and cross-team coordination.

• Architect and lead development of physical design methodologies and automation flows for complex SubSystems.
• Provide deep technical leadership for RTL-to-GDSII implementation including synthesis, floorplanning, place-and-route, clock tree synthesis and timing closure.
• Perform hands-on SubSystem hardening and deliver reference floorplans and fully synthesized, timing-closed SubSystem partitions to the SOC team.
• Coordinate with DFT and SOC teams for DFT insertion and SOC-level timing closure.
• Work with RTL teams to implement ECOs, bug fixes, and timing fixes.
• Serve as a technical advisor across multiple projects and resolve complex implementation challenges.
• Collaborate with global cross-functional teams including RTL, verification, and CAD to ensure cohesive execution.
• Mentor and coach senior and junior engineers to promote best practices.
• Evaluate and drive adoption of EDA tools and automation in partnership with internal CAD and external vendors.
• Represent the physical design team in strategic technical discussions and roadmap planning.

Requirements

Must-have technical skills are listed first; preferred skills follow.

• Must-have: Proven experience in synthesis, floorplanning, place-and-route, clock tree synthesis, and timing closure for large, complex designs.
• Must-have: Extensive experience with Verilog and RTL quality checks.
• Must-have: Hands-on scripting experience (Perl, Python or similar) for automation.
• Must-have: Track record of delivering production-quality designs on aggressive schedules; strong communication and teamwork skills.
• Nice-to-have: Domain experience with SoC architecture, processor cores, memory, PCIe/CXL.
• Nice-to-have: Experience with Ethernet, security and peripheral interfaces.
• Nice-to-have: Experience with memory generation and working with advanced foundries/process nodes (5nm, 3nm, 2nm).

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering or related field with 10–15 years' relevant experience; or Master's degree or PhD in Computer Science, Electrical Engineering or related field with 5–10 years' relevant experience; or equivalent professional experience in lieu of a formal degree.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.