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Principal Physical Design Engineer, STA

Broadcom
November 2, 2026
Full-time
On-site
San Jose, California, United States
$143,800 - $230,000 USD yearly
Physical Design Jobs, Level - Senior

Job Title

Principal Physical Design Engineer, STA

Role Summary

Lead full-chip Static Timing Analysis (STA) for Broadcom's ASIC Products Division, ensuring timing closure for advanced-node, large-scale ASICs and multi-die integrations. Drive AI-assisted STA automation, collaborate with RTL, physical design, and DFT teams, and deliver sign-off-quality timing results.

Experience Level

Senior - 12+ years of hands-on ASIC STA and timing closure experience.

Responsibilities

Primary responsibilities include ensuring timing sign-off and improving STA flows and infrastructure.

  • Own final timing closure across PVT corners and author/maintain SDC for functional and test modes.
  • Deploy AI/ML automation within STA flows to reduce runtime and optimize shared compute infrastructure.
  • Triage timing violations using automated workflows and data-mining to isolate root causes and remove marginalities.
  • Drive timing ECOs and collaborate with RTL, Physical Design, and DFT teams to optimize performance, power, and area (PPA).
  • Apply advanced OCV, SI, and IR-drop concepts to timing sign-off and closure strategies.

Requirements

Must-have technical skills and experience.

  • Expert proficiency with sign-off tools (PrimeTime, Tempus).
  • Deep experience with multi-mode multi-corner (MMMC) timing, OCV management, and full-chip STA signoff.
  • Strong scripting skills (Tcl, Python, Perl, Shell) for automation and reporting.
  • Proven experience using AI/plugins and data-mining to accelerate timing closure and reduce runtimes.
  • Ability to analyze complex clock networks, cross-die timing paths, and coordinate ECOs at scale.
  • Excellent problem-solving, communication, and cross-functional collaboration skills.

Nice-to-have:

  • Experience with 2.5D/3D chiplet integration (CoWoS, HBM) and very large die implementations.
  • Familiarity with infrastructure/cluster optimization for large-scale EDA runs.

Education Requirements

Bachelor’s degree in Electrical or Computer Engineering is specified. The posting also specifies 12+ years of hands-on ASIC STA and timing closure experience.


About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.

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Date Posted: 2026-10-30