Principal Physical Design Engineer
QualcommJob Title
Principal Physical Design Engineer
Role Summary
Join the ASIC/Physical Design team to define, design, optimize, verify, and deliver complex IP blocks and SoCs for high-performance, low-power products. Work with cross-functional engineering teams to translate system requirements into implementable physical design and layout solutions.
Experience Level
Senior / Principal level. Typical experience expected is multi-year senior ASIC/physical-design work; minimum relevant experience is described in Requirements and Education Requirements. Preferred candidates have extensive hands-on architecture and implementation experience (multiple years; see Preferred Qualifications).
Responsibilities
Accountabilities for this role include advanced architecture, implementation, and cross-team execution for multiple complex blocks or SoCs.
- Define and model high-level architectures, circuit specifications, and logic designs to meet system requirements.
- Lead physical-design implementation: RTL-to-GDS flow, synthesis, place-and-route, timing closure, and power optimization.
- Apply custom circuit design and layout flow where required; support mixed digital/analog design tasks.
- Develop and execute verification, validation, and integration plans for IP and SoC level deliverables.
- Provide technical leadership and mentorship; review designs and documentation from other engineers.
- Collaborate with software, hardware architecture, product management, and program teams to align implementation strategy with product goals.
- Produce and review detailed technical documentation for complex EDA/IP/ASIC projects.
Requirements
Core technical and professional requirements. See Education Requirements for degree and degree-year equivalencies.
- Minimum: substantial experience in ASIC design, verification, validation, integration, or related work (see Education Requirements for specific year expectations).
- Deep knowledge of the full physical-design flow: synthesis, place-and-route, timing/power analysis, and signoff.
- Experience with RTL-to-GDS flows and common EDA tools; familiarity with Virtuoso or equivalent for custom design is a plus.
- Practical experience with design verification methods and integration strategies.
- Proficiency with scripting and programming for automation (several years preferred).
- Ability to make high-impact technical decisions, communicate complex topics clearly, and interact with senior leadership; may include supervising direct reports.
- Strong technical writing skills and ability to produce detailed design documentation.
- Nice-to-have: prior experience designing multiple complex blocks/SoCs, working across package/IC boundaries, and extensive architecture-level contributions.
Education Requirements
Minimum/typical degrees: Bachelor's degree in Science, Engineering, or related field (with approximately 8+ years relevant ASIC experience), Master's degree in Science/Engineering or related field (with approximately 7+ years), or PhD in Science/Engineering or related field (with approximately 6+ years). Preferred fields include Electrical/Electronic Engineering, Computer Engineering, or Computer Science. Equivalent practical experience is accepted where indicated.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
