Principal Physical Design Engineer

Job Title

Principal Physical Design Engineer

Role Summary

Lead physical implementation of complex SoCs and digital blocks from RTL to GDSII. Drive floorplanning, power planning, place-and-route, clock tree synthesis, timing closure, and physical verification to deliver manufacturable, high-performance silicon.

Act as a technical leader: define physical design methodology, improve automation, and mentor engineers across architecture, RTL, circuit design, and verification teams to ensure successful tape-out.

Experience Level

Senior - requires 7+ years of relevant ASIC physical design experience.

Responsibilities

Primary responsibilities include owning physical implementation and ensuring signoff-ready designs.

• Own RTL-to-GDSII execution for SoCs or complex digital blocks.
• Lead floorplanning, bump planning, power grid design, and clock tree synthesis to meet PPA goals.
• Resolve timing, congestion, EM/IR, and signal-integrity issues with frontend designers.
• Perform signoff flows: static timing analysis (STA), physical verification, DRC/LVS resolution.
• Develop and maintain automation and methodologies using scripting (Tcl, Python, Perl).
• Coordinate cross-functionally with architects, logic, and analog teams for tapeout readiness.

Requirements

Must-have technical skills and experience for successful candidates.

• 7+ years of ASIC physical design experience.
• Proven tapeout experience in advanced nodes (for example 7nm, 5nm, 3nm).
• Advanced proficiency with industry EDA tools (examples: Cadence Innovus, Tempus, Voltus, Pegasus, Calibre).
• Expertise in physically aware synthesis, power-domain analysis, and EM/IR mitigation.
• Strong STA and physical verification experience; able to fix DRC/LVS issues.
• Proficient scripting skills for flow automation (Tcl, Python, or Perl).
• Demonstrated ability to lead projects and mentor junior engineers.

Education Requirements

The posting references "depending on degree level" in relation to experience expectations but does not specify particular degrees, fields of study, certifications, or explicit equivalent-experience language. No specific degree types (e.g., BS, MS, PhD) or disciplines are listed.

About the Company

Company: Celero Communications

Headquarters: Ottawa, Ontario, Canada

Designs and develops optical transceivers and ASIC solutions for next-generation optical modems, focusing on digital ASIC/RTL design, verification, and optical communication technologies.