Principal Physical Design Engineer
ArterisIPJob Title
Principal Physical Design Engineer
Role Summary
Work on generation, implementation, and verification of physical design collateral and CAD flows for configurable SoC IP. The role focuses on physical implementation quality, debugging tool-chain and integration issues, and improving methodologies across multiple EDA toolchains.
You will collaborate with hardware and software engineers and internal stakeholders to ensure reliable, automated physical implementation flows for production IP products.
Experience Level
Senior — typically requires 5+ years of experience in digital IC design and physical implementation.
Responsibilities
Contribute to development, validation, and maintenance of physical implementation flows and related automation.
- Develop, maintain, and debug physical implementation flows and constraints using EDA tools (Cadence, Synopsys, etc.).
- Define, document, and execute verification tests and system-level coverage for implementation flows.
- Analyze implementation quality metrics and validate results across multiple configurations.
- Debug implementation issues, regressions, and tool-flow related problems.
- Improve methodologies, implementation strategies, and automation aligned with modern semiconductor design practices.
- Collaborate with hardware and software teams to resolve compatibility and interface issues.
- Support process documentation and engineering best practices; interact with stakeholders to define requirements and support flow evolution.
Requirements
Must-have technical skills and experience for successful performance in this role.
- 5+ years experience in digital IC design and physical implementation.
- Strong knowledge of physical implementation flows and EDA toolchains; proficiency in Design Compiler/Fusion Compiler or Genus is required.
- Expertise in physical design debugging and implementation analysis.
- Strong understanding of timing constraints, STA concepts, and timing analysis methodologies.
- Experience with hardware description and scripting languages, including Python, RTL, and TCL.
- Strong analytical, debugging, and problem-solving skills; effective written and verbal communication.
- Ability to work autonomously in a fast-paced engineering environment.
Nice-to-have:
- Experience with highly configurable IP or SoC integration flows.
- Familiarity with verification methodologies and coverage-driven validation.
- Experience improving CI/CD or automation for semiconductor implementation environments.
- Exposure to advanced process nodes and low-power implementation techniques.
Education Requirements
Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Compensation
Estimated base salary: 050,000 to 070,000 annually (range provided by employer).
About the Company
Company: ArterisIP
Headquarters: Montigny-le-Bretonneux, France
Provider of configurable on-chip interconnect IP and network-on-chip (NoC) solutions for system-on-chip (SoC) integration, offering interconnect fabrics, IP blocks, verification tools and engineering support to semiconductor and system companies.
