Principal Physical Design Engineer

Job Title

Principal Physical Design Engineer

Role Summary

Principal-level individual contributor on Microsoft Silicon within the Cloud Hardware and Infrastructure Engineering organization. The role focuses on physical implementation (place-and-route, STA, PV, FEV, ECOs, clocking, IR-drop/EM) for next-generation AI SoCs and related blocks/subchips.

Work with cross-functional teams to define and deliver tools, flows, methodologies, and quality checks that enable tapeouts and high-volume manufacturing of cloud hardware.

Experience Level

Senior / Principal. Typically requires extensive hands-on physical design and tapeout experience (generally 8+ years of relevant technical engineering experience or equivalent).

Responsibilities

Primary responsibilities include execution and leadership of physical design tasks and delivery of tool/flow/methodology for block, sub-chip, and full-chip implementation.

• Lead place-and-route convergence recipe development for blocks, subsystems, and subchips.
• Perform static timing analysis, timing closure, and timing ECO implementation with minimal physical impact.
• Develop and implement physical verification, formal equivalence verification, and functional ECO methodologies.
• Design and implement global clocking schemes at SOC and subchip levels.
• Assess and mitigate IR-drop and electromigration (EM) issues; integrate EM/IR flows into signoff process.
• Install, validate, and manage internal and external IP collateral and PD infrastructure artifacts.
• Conduct physical design reviews, identify/resolution of issues, and mentor junior engineers.
• Stay current with industry trends and introduce improvements to PD processes and tool usage.

Requirements

Must-have skills and conditions for the role.

• Proven track record delivering physical design projects and leading PD execution (block/subchip/full-chip).
• Deep practical experience in place-and-route convergence, STA, timing ECOs, PV, FEV, and clocking construction.
• Strong scripting ability (TCL, Python) to automate flows and PD infrastructure tasks.
• Experience with foundry tech files, rule decks, and integrating them into PD flows.
• Ability to pass Microsoft Cloud Background Check and meet export-control eligibility requirements.
• Excellent problem solving and communication skills; experience mentoring or leading engineers.

Nice-to-have:

• Experience with tapeouts of complex ASICs in leading-edge process nodes.
• Familiarity with EDA tools such as Synopsys Fusion Compiler, PrimeClosure, PrimeTime, Formality, VCLP, Star-RC, RedHawk SC, Cadence Innovus, and Siemens Calibre.

Education Requirements

Doctorate (PhD) in Electrical Engineering, Computer Engineering, Computer Science, or related field (plus 3+ years technical engineering experience), OR Master's degree in those fields (plus 6+ years), OR Bachelor's degree in those fields (plus 8+ years), OR equivalent practical experience. Fields explicitly mentioned: Electrical Engineering, Computer Engineering, Computer Science, or related technical disciplines.

About the Company

Company: Microsoft

Headquarters: Redmond, Washington, United States

Microsoft is a global technology company that develops and sells software, services, devices, and solutions. Known for its Windows operating system, Office suite, and Azure cloud platform, Microsoft aims to empower individuals and organizations around the world to achieve more. The company fosters a culture of innovation and inclusion, focusing on delivering trusted experiences to customers and partners globally.