Principal Physical Design Engineer

Job Title

Principal Physical Design Engineer

Role Summary

The Principal Physical Design Engineer will develop and maintain RTL-to-GDS place-and-route (P&R) flows and methodology for advanced ASIC designs. The role partners with RTL, analog/mixed-signal, EDA, PDK/library, and signoff teams to deliver scalable, robust physical implementation flows and high-quality silicon.

Experience Level

Senior - typically requires 7–10+ years of experience in ASIC physical design flows or physical design methodology.

Responsibilities

Primary responsibilities include flow development, implementation support, signoff quality, and cross-team collaboration.

• Develop, maintain, and enhance RTL-to-GDS flows using Cadence Innovus and Synopsys Fusion Compiler.
• Create repeatable methodologies for floorplanning, placement, CTS, routing, and optimization.
• Automate flow steps using Tcl, Python, Make-based infrastructures, and Linux tooling.
• Provide hands-on support for floorplan definition, clock topology, power grid planning, placement optimization, timing closure, IR/EM mitigation, and DRC fixing.
• Debug tool convergence issues and resolve signoff discrepancies across STA, LVS, DRC, and extraction.
• Drive correlation improvements between implementation tools and signoff tools (PrimeTime, StarRC, Voltus, RedHawk, Calibre).
• Collaborate with EDA, PDK/library, architecture, and design teams to evaluate tools and scale flows for next-generation technologies.

Requirements

Must-have technical skills and preferred additions are listed below.

• Must-have:
  • 7–10+ years in ASIC physical design flows or methodology (P&R development or implementation).
  • Hands-on experience with Cadence Innovus and/or Synopsys Fusion Compiler.
  • Strong knowledge of floorplan, placement, CTS, routing, ECO flows, and timing concepts (setup/hold, OCV/AOCV/POCV).
  • Experience with power/thermal integrity (IR drop, EM) and DRC/LVS signoff flows.
  • Proven ability to troubleshoot complex tool, flow, or methodology issues across PD and signoff.
  • Scripting skills in Tcl and Python; familiarity with Linux shell and Make-based automation.
• Nice-to-have:
  • Experience with advanced process nodes (7 nm, 5 nm, or below).
  • Familiarity with UPF/low-power flows, hierarchical P&R, and multi-clock-domain designs.
  • Experience with version control (Git/Perforce) and CI automation.
  • Knowledge of extraction and signoff tools (StarRC, PrimeTime, Voltus, RedHawk, Calibre).

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Hewlett Packard Enterprise

Headquarters: Spring, TX, United States

Global enterprise technology company delivering hybrid cloud, edge-to-cloud platforms, servers, storage, networking, and IT services to help organizations build, run, and secure applications and infrastructure at scale.