Principal Package Design Engineer

Job Title

Principal Package Design Engineer

Role Summary

Lead the design, development, and qualification of advanced semiconductor packaging solutions for high-performance products. Work across design, manufacturing, suppliers, and quality teams to define package architecture, assembly flows, and qualification plans that meet electrical, thermal, mechanical, reliability, and cost targets.

Experience Level

Senior — typically 5+ years of experience in advanced semiconductor or electronics packaging and system integration.

Responsibilities

Accountable for technical leadership across package design, qualification, and production ramp for new products.

• Lead design and qualification of advanced packaging types (flip-chip, WLP/FOWLP, panel-level, 2.5D/3D, SiP, BGA/CSP, W2W/D2W heterogeneous bonding).
• Define package architecture considering electrical, thermal, mechanical, reliability, and cost requirements.
• Drive OSAT and substrate vendor selection, development, and process transfer for NPI.
• Collaborate with IC design, substrate, board, thermal, reliability, applications, and manufacturing teams to ensure compatibility and performance.
• Oversee package layout reviews, stack-up definition, material selection, and interconnect strategy.
• Perform and guide simulations and analyses: signal/power integrity, thermal, mechanical stress/warpage, and DFM.
• Develop assembly flows and process specifications for manufacturing partners and OSATs.
• Lead qualification activities including DOE planning, failure analysis, reliability testing, and production issue resolution.
• Collaborate with suppliers on material evaluation, process improvement, and yield optimization.
• Document package specifications, design rules, process flows, and technical reports; mentor junior engineers.

Requirements

Must-have skills and experience required to perform this role.

• Minimum 5+ years of hands-on experience in advanced semiconductor or electronics packaging and system integration.
• Proven experience with advanced packaging technologies, materials, and assembly processes relevant to high-performance products.
• Deep understanding of thermal, mechanical, and electrical interactions in package design and proven experience setting up and running simulations and models.
• Experience with package reliability testing, qualification methods, and failure analysis.
• Strong skills with CAD and simulation tools and workflow for package design.
• Experience working with OSATs, substrate vendors, assembly houses, and semiconductor supply chains.
• Proven troubleshooting skills, ability to drive root cause/corrective actions, and strong cross-functional project leadership and communication.

Nice-to-have

• Experience with power semiconductor devices and packaging (Si/SiC/GaN MOSFETs, power modules, IPMs) and applications in data center, automotive, industrial, or HPC/AI hardware.
• Hands-on use of package design and simulation tools such as Cadence Allegro Package Designer, SolidWorks, ANSYS, COMSOL, JMP/Minitab.
• Knowledge of JEDEC, IPC, and semiconductor qualification standards and methods.
• Experience with W2W, D2W, D2D heterogeneous integration and chiplet-based packaging.

Education Requirements

MSc or PhD in Electrical Engineering, Materials Science, Mechanical Engineering, Chemical Engineering, or a related engineering field (as stated in the source).

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.