Principal Package Design Engineer

Job Title

Principal Package Design Engineer

Role Summary

Lead development and qualification of advanced semiconductor packaging solutions, focusing on architecture, assembly processes, thermal/mechanical reliability and cross-functional integration from concept through production. Position partners with IC design, manufacturing, suppliers and quality teams to deliver high-performance, manufacturable packages.

Experience Level

Senior-level — typically 5+ years' experience in semiconductor or advanced electronics packaging.

Responsibilities

Provide technical leadership for package design, qualification and production ramp. Key responsibilities include:

• Lead design and qualification of advanced packages (flip-chip, chip embedding, WLP/FOWLP, panel-level, 2.5D/3D, SiP, BGA/CSP).
• Define package architecture to meet electrical, thermal, mechanical, reliability and cost requirements.
• Oversee package layout reviews, stack-up definition, material selection and interconnect strategy.
• Perform and guide simulations and analysis: signal/power integrity, thermal performance, mechanical stress/warpage and DFM.
• Develop assembly flows and process requirements with OSATs and manufacturing partners.
• Plan and lead package qualification activities, DOE, failure analysis and reliability testing.
• Resolve packaging issues during NPI, qualification and production ramp; drive root-cause and corrective actions.
• Collaborate with IC design, substrate, board, thermal, reliability and supplier teams to optimize yield and performance.
• Create and maintain package specifications, design rules, process documentation and technical reports.
• Mentor junior engineers and provide technical leadership across packaging initiatives.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• 5+ years' experience in semiconductor or advanced electronics packaging.
• Deep knowledge of advanced packaging technologies, materials and assembly processes.
• Experience with package reliability testing and qualification methods and standards.
• Strong understanding of thermal, mechanical and electrical interactions in package design.
• Experience working with OSATs, substrate vendors and assembly houses.
• Proven ability to troubleshoot packaging failures and lead root-cause/corrective actions.
• Project leadership experience and strong cross-functional communication skills.

Nice-to-have:

• Experience with power devices and packaging (Si/SiC/GaN), power modules and automotive or high-performance computing/AI hardware applications.
• Hands-on experience with Cadence Allegro Package Designer, SolidWorks, ANSYS, COMSOL, JMP/Minitab.
• Familiarity with JEDEC and IPC standards; experience with heterogeneous integration and chiplet-based packaging (W2W, D2W, D2D).

Education Requirements

MSc or PhD in Electrical Engineering, Materials Science, Mechanical Engineering, Chemical Engineering or a related technical field (Master’s/PhD explicitly listed as preferred).

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.