Principal Package Design Engineer

Job Title

Principal Package Design Engineer

Role Summary

Lead development and integration of advanced semiconductor packaging solutions for high-performance products. Focus areas include package architecture, assembly processes, thermal and mechanical reliability, qualification, and cross-functional collaboration with design, product engineering, manufacturing, suppliers, and quality teams.

Experience Level

Senior-level (Principal). Recommended: 5+ years' experience in advanced semiconductor or electronics packaging.

Responsibilities

Accountable for architecture, development, qualification, and production ramp of advanced packaging technologies.

• Lead design, development, and qualification of packaging solutions such as flip-chip, WLP/FOWLP, panel-level, 2.5D/3D, SiP, BGA/CSP, and heterogeneous bonding.
• Define package architecture considering electrical, thermal, mechanical, reliability, and cost requirements; perform hands-on simulation and modeling.
• Drive OSAT and substrate vendor selection, development, and NPI readiness.
• Coordinate with IC design, substrate, board, thermal, reliability, applications, and manufacturing teams to ensure compatibility and performance.
• Oversee package layout reviews, stack-up definition, material selection, and interconnect strategy.
• Perform and guide simulations and analysis: signal/power integrity, thermal performance, mechanical stress/warpage, and DFM.
• Develop assembly flows and process requirements for OSATs and manufacturing partners; lead qualification, DOE planning, failure analysis, and reliability testing.
• Resolve packaging issues during prototype builds, qualification, and production ramp; lead root-cause and corrective actions.
• Document package specifications, design rules, process flows, and technical reports; mentor junior engineers.

Requirements

Must-have technical skills and experience for successful performance in the role.

• 5+ years' experience in advanced semiconductor or electronics packaging and system integration.
• Hands-on knowledge of advanced packaging technologies, materials, assembly processes, and system-level integration for AI infrastructure and data-center power management.
• Deep understanding of thermal, mechanical, and electrical interactions in package design; experience setting up models and running simulations.
• Strong background with CAD and simulation tools for package design.
• Experience with package reliability testing, qualification standards, and failure analysis.
• Experience working with OSATs, substrate vendors, and assembly houses.
• Proven troubleshooting skills, project leadership, and cross-functional communication.

Nice-to-have:

• Experience with power semiconductors and packaging for Si/SiC/GaN MOSFETs, power modules, and intelligent power modules.
• Experience with high-performance computing, AI/ML hardware, or mobile product power solutions.
• Hands-on experience with Cadence Allegro Package Designer, SolidWorks, ANSYS, COMSOL, JMP/Minitab.
• Knowledge of JEDEC and IPC standards and semiconductor qualification methods.
• Experience in W2W, D2W, D2D heterogeneous integration and chiplet-based packaging.

Education Requirements

MSc or PhD in Electrical Engineering, Materials Science, Mechanical Engineering, Chemical Engineering, or a related field (as stated in the posting).

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.