Principal NoC IP Micro-Architect

Job Title

Principal NoC IP Micro-Architect

Role Summary

Lead design and micro-architecture for Network-on-Chip (NoC) IPs and related FPGA IP subsystems for integration into full-chip designs. Own RTL design, simulation, verification oversight, and collaboration with physical implementation to meet power, performance, and area targets.

Provide technical leadership for the NoC team, drive architecture decisions, deploy automation/AI to improve development efficiency, and mentor junior engineers.

Experience Level

Senior — requires 15+ years of related experience in ASIC/FPGA IP or system design.

Responsibilities

Primary responsibilities include designing, implementing, verifying, and delivering NoC IP and supporting models while leading the team technically.

• Develop RTL, logic design, and simulation models for NoC IP and related FPGA IP/subsystems.
• Define block architecture and microarchitecture; create prototypes and system requirement specifications.
• Prepare logic diagrams and production-quality RTL code to implement design and test specifications.
• Deliver software models for device bring-up, including functional, timing, and power behavior.
• Apply RTL implementation techniques and partner with physical implementation to meet power, performance, and area goals.
• Use advanced EDA flows and tools for timing constraint verification, lint, CDC/RDC, and DFT.
• Review verification plans, oversee verification execution, and resolve failing RTL tests.
• Provide technical leadership: groom team members, guide design reviews, anticipate risks, and drive mitigation to meet schedule and quality targets.
• Deploy automation and AI tools to improve development productivity and reduce manual effort.

Requirements

Required technical skills, tools experience, and leadership capabilities. Education details are summarized separately below.

• Must-have: 15+ years of relevant industry experience in RTL/IP development and micro-architecture for NoC or similar interconnect IPs.
• Must-have: Strong expertise in SystemVerilog, simulation (e.g., VCS/Synopsys), lint, and synthesis methodologies.
• Must-have: Proficiency in scripting and programming: C/C++, Python, Perl, Tcl, and Unix shell.
• Must-have: Deep familiarity with EDA flows: timing constraints, CDC/RDC analysis, RTL linting, and DFT practices.
• Must-have: Proven ability to integrate RTL with physical implementation teams to meet PPA targets.
• Must-have: Strong communication, cross-team collaboration, problem-solving skills, and experience mentoring engineers.
• Nice-to-have: FPGA design and programming experience.
• Nice-to-have: RTL validation experience and prior use of AI/automation to accelerate IP development.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field. The posting specifies 15+ years of related working experience.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.