Principal NoC IP Micro-Architect

Job Title

Principal NoC IP Micro-Architect

Role Summary

Lead the architecture, microarchitecture, RTL design, and technical delivery of scalable Network-on-Chip (NoC) IP integrated into next-generation FPGA platforms. Work cross-functionally with architecture, design, verification, software, physical design, and product teams to meet PPA, scalability, and reliability goals.

This is a high-visibility technical leadership role focused on system-level interconnect design, performance optimization, and team mentorship.

Experience Level

Senior — Principal level. The posting specifies 15+ years of related experience with deep technical leadership responsibilities.

Responsibilities

Primary responsibilities include end-to-end IP architecture, RTL delivery, verification oversight, and technical leadership.

• Define architecture and microarchitecture for NoC IP and related interconnect subsystems.
• Design, code, and simulate RTL (SystemVerilog) and create logic diagrams and prototypes.
• Develop models and software for device bring-up covering functionality, timing, and power.
• Apply RTL implementation techniques to meet power, performance, and area (PPA) targets in partnership with physical implementation teams.
• Specify and run simulation, lint, CDC, timing, synthesis, and DFT flows; resolve RTL/verification issues.
• Perform performance modeling and system-level optimization of interconnect fabrics.
• Drive automation and incorporate AI/ML tools to improve development efficiency.
• Provide technical leadership, mentor engineers, and proactively remove design roadblocks to meet schedule and quality goals.

Requirements

Must-have technical skills and experience; nice-to-have items listed separately.

• Must-have: Deep expertise in NoC/SoC interconnect architectures and scalable interconnect design.
• Must-have: ≥10 years experience with RTL development using SystemVerilog and experience with industry simulators (e.g., VCS/Synopsys), lint, and synthesis flows.
• Must-have: Strong software/scripting skills: C/C++, Python, Perl, TCL, and Unix shell scripting for tool automation and models.
• Must-have: Proven experience with timing constraint verification, CDC/RDC analysis, and DFT methodologies.
• Nice-to-have: Significant FPGA design experience and RTL validation background.
• Nice-to-have: Experience applying AI/automation to the development process (listed as a strong plus).

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field is specified. The posting requires 15+ years of related working experience.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.