Principal Modem PHY IP Design Verification Engineer - Terawave

Job Title

Principal Modem PHY IP Design Verification Engineer - Terawave

Role Summary

Lead verification of modem PHY IP for the TeraWave satellite communications program. Develop verification strategies, build scalable verification environments, and ensure delivery of high-quality modem PHY IP for next-generation wireless ASIC platforms.

Work closely with PHY architects, RTL designers, systems, firmware, FPGA, and validation teams across simulation, emulation, prototyping, and silicon bring-up.

Experience Level

Senior / Principal level. Requires a seasoned verification engineer; the role expects around 10+ years of relevant experience.

Responsibilities

Primary responsibilities include planning and executing verification for modem PHY IP and its integration into subsystems.

• Define and execute verification strategies and plans for PHY IP and subsystem integration.
• Design and maintain block-level and subsystem-level verification environments using industry-standard methodologies.
• Create testbenches, stimulus, checkers, scoreboards, assertions, and coverage models.
• Verify modulation/demodulation, timing/frequency synchronization, channel estimation/equalization, MIMO/beamforming, FEC integration, and control/config interfaces.
• Correlate RTL behavior with floating-point, fixed-point, or bit-accurate reference models from algorithm and architecture teams.
• Define and track functional, code, assertion, and scenario coverage; develop constrained-random and directed tests for feature, stress, and corner-case validation.
• Identify, debug, and root-cause design and integration issues; support throughput, latency, buffering, and protocol timing verification.
• Contribute to regression automation, CI flows, verification infrastructure, FPGA prototyping, emulation, and post-silicon debug.
• Document verification plans, test results, coverage status, and quality metrics; coordinate with external partners as needed.

Requirements

Must-have technical skills and experience for the role.

• Approximately 10+ years of digital/ASIC/SoC or modem/baseband verification experience.
• Strong experience with SystemVerilog and UVM-based verification methodologies.
• Experience developing verification environments for complex DSP, modem, or communications IP.
• Familiarity with OFDM or single-carrier systems, synchronization, channel estimation/equalization, FEC (LDPC, Polar, Turbo, BCH), MIMO/beamforming, and fixed-point/quantized signal processing.
• Proficiency with scripting and automation (Python, Perl, shell) and strong RTL/testbench debugging skills.
• Ability to work closely with design, architecture, systems, firmware, FPGA, and validation teams in a fast-paced environment.

Nice-to-have:

• Experience with MATLAB, C/C++ or Python-based algorithm reference models.
• Familiarity with assertions, formal verification, lint, CDC/RDC, low-power verification, emulation, FPGA prototyping, and post-silicon validation/debug.
• Experience with mmWave / sub-THz / Terahertz systems, satellite/space communications, 5G/6G, or high-throughput wireless backhaul/mesh systems.
• Knowledge of RF/system impairments (phase noise, frequency offset, nonlinearities, channel effects).

Education Requirements

Minimum: Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. Preferred: Master’s degree in Electrical Engineering, Computer Engineering, Signal Processing, Communications, or related field.

About the Company

Company: Blue Origin

Headquarters: Kent, Washington, United States

Blue Origin is an American aerospace company developing technologies for spaceflight, including reusable launch vehicles, orbital and suborbital systems, and space infrastructure for commercial and government customers.