Principal Mixed Signal Design Verification, Team Lead

Job Title

Principal Mixed Signal Design Verification, Team Lead

Role Summary

Lead the mixed-signal design verification team responsible for verification of Power IC products (motor drivers, PMICs, gate drivers) from architecture through tape-out. The role combines hands-on verification engineering, methodology development, and team leadership, based in Richardson, TX.

Experience Level

Senior - typically requires 8+ years of experience in mixed-signal design verification and leadership.

Responsibilities

Accountable for verification strategy, team execution, and delivery of tape-out-ready verification results.

• Lead, mentor, and grow a team of mixed-signal verification engineers.
• Define and execute full-chip verification plans and schedules; track regression and coverage metrics to sign-off.
• Design and implement scalable SystemVerilog/UVM testbenches, including scoreboards, drivers, monitors, and class objects.
• Integrate requirements traceability into verification tests and maintain Verification Reports for tape-out.
• Develop assertions (SVA) to enforce analog and digital boundaries and support ISO 26262 hardware safety verification.
• Create high-fidelity behavioral models from analog schematics for simulation in Cadence mixed-signal environments.
• Establish automated regression flows and manage verification workflows and issues in GitLab.
• Partner with Systems and Design teams on architecture, feasibility studies, and pre-silicon planning.

Requirements

Must-have technical skills and proven delivery in mixed-signal verification; leadership and automation experience expected.

• 8+ years of hands-on mixed-signal design verification experience, with a record of full-chip verification and tape-out sign-off.
• Expertise in SystemVerilog, UVM methodologies, and SVA assertions.
• Proficiency with scripting for automation (Python, Bash, Perl or similar).
• Strong familiarity with Cadence mixed-signal simulation flows and tool usage.
• Deep understanding of analog and mixed-signal blocks and the ability to guide creation of behavioral models (PLLs, charge pumps, bandgaps, ADCs/DACs, etc.).
• Experience translating requirements into automated verification tests; knowledge of requirements tools (Jama) and safety compliance (ISO 26262) verification is required.
• Practical experience using GitLab or similar engineering interfaces for regression tracking and CI.
• Proven ability to coach and develop junior-to-mid-level engineers into independent contributors.
• Nice-to-have: prior experience with power-related topologies (motor drivers, PMICs, gate drivers).

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Microelectronics, or a closely related technical field.

About the Company

Company: Allegro MicroSystems

Headquarters: Manchester, New Hampshire, USA

Global semiconductor company with over 30 years of innovation, developing semiconductor devices and design enablement tools. Allegro focuses on device development, foundry partnerships, IP characterization, and design automation to support product roadmaps and technology advancement.