Principal Memory Subsystem Engineer (Design or DV)

Job Title

Principal Memory Subsystem Engineer (Design or DV)

Role Summary

Principal engineer responsible for leading design or design verification of high-performance memory subsystems in SoCs used for cloud and AI infrastructure. Works across architecture, RTL, verification, physical design, firmware, and post-silicon teams to deliver scalable, high-efficiency solutions.

Experience Level

Senior (Principal) — expects an experienced engineer with multi-year leadership and technical delivery in SoC design or verification (see Education Requirements for formal experience equivalencies).

Responsibilities

Lead technical execution and cross-functional delivery for memory subsystem design or verification.

• Provide technical leadership from architecture and microarchitecture through silicon bring-up.
• Lead design, integration, and verification of complex SoC subsystems focused on memory: bandwidth, latency, utilization, power, and efficiency.
• Collaborate with Architecture, RTL Design, DV, PD, DFT, Firmware, and Post-Silicon teams to resolve system-level issues.
• Drive IP/component reuse and scalable subsystem architectures across projects.
• Specify microarchitecture, develop/integrate RTL (Verilog/SystemVerilog), and manage synthesis, timing constraints, floor-planning, and PPA trade-offs.
• Lead verification strategy and test plans, including UVM constrained-random environments, scoreboards, assertions, and coverage closure.
• Debug complex issues across simulation, emulation, and silicon and implement effective corrective actions.
• Execute in an Agile environment: sprint planning, code reviews, feature deployment, and continuous process improvement.

Requirements

Must-have technical skills and constraints for the role. Degree and specific experience-year combinations are summarized in Education Requirements below and have been omitted here to avoid duplication.

• Deep expertise in digital logic design, microarchitecture specification, and RTL development in Verilog/SystemVerilog.
• Proven experience in synthesis, timing closure, power/performance/area trade-offs, and post-silicon debug.
• Strong verification skills: UVM, constrained-random testbenches, functional coverage, assertions, and familiarity with C++ test components.
• Hands-on experience with memory-related technologies and subsystems (HBM, PCIe, DMA engines, interconnect fabrics, NoC, AMBA AXI/CHI).
• Experience with simulation, emulation, and silicon bring-up workflows and tooling; strong debugging skills.
• Experience leading cross-functional, distributed engineering teams and mentoring engineers.
• Scripting proficiency (Python, Perl, or similar) and familiarity with design-quality tools (lint, CDC, formal where applicable).
• Ability to meet Microsoft security screening and export-control eligibility requirements; access to export-controlled information may be required.
• Preferred: formal property verification experience and multiple product-cycle verification delivery.

Education Requirements

One of the following is expected: Doctorate (PhD) in Electrical Engineering, Computer Engineering, Computer Science, or a related field plus 3+ years technical engineering experience; OR Master’s degree in those fields plus 6+ years experience; OR Bachelor’s degree in those fields plus 8+ years experience; OR equivalent practical experience. The posting also specifies that proof of citizenship or lawful residency may be required to access export-controlled information.

About the Company

Company: Microsoft

Headquarters: Redmond, Washington, United States

Microsoft is a global technology company that develops and sells software, services, devices, and solutions. Known for its Windows operating system, Office suite, and Azure cloud platform, Microsoft aims to empower individuals and organizations around the world to achieve more. The company fosters a culture of innovation and inclusion, focusing on delivering trusted experiences to customers and partners globally.