Principal Memory Controller Architect

Job Title

Principal Memory Controller Architect

Role Summary

The Principal Memory Controller Architect will design and drive next-generation custom memory controller IP to support Microsoft SoCs (Cobalt) and Azure platform workloads. The role partners with product, hardware and software architects, verification, vendors, performance modeling, and manufacturing teams to deliver high-performance, efficient, and reliable memory subsystems.

Experience Level

Senior-level (Principal). Experience expectations per posted equivalencies: PhD +7 years, Master’s +10 years, Bachelor’s +12 years, or equivalent practical experience. See Education Requirements for full degree-equivalence details.

Responsibilities

Key responsibilities include:

• Architect and develop memory controller IP for server-grade SoCs.
• Evaluate memory technology roadmaps (DDR5, DDR6, LPDDR, HBM, CXL-based memory, RDIMM/MRDIMM variants, and emerging memory types) and recommend architecture trade-offs.
• Collaborate with micro-architects, verification, validation, vendors, and performance teams to drive features into production.
• Develop cycle-approximate performance models and analyze SOC/platform results against Azure workloads.
• Identify full-stack optimization opportunities across the memory hierarchy with platform and architecture teams.
• Work with vendors to evaluate IP quality, risks, and integration feasibility.
• Communicate architecture decisions and produce specifications for implementation and verification teams.

Requirements

Must-have technical skills and conditions:

• Proven experience architecting memory controllers and defining controller features for production SoCs.
• Knowledge of DDR family technologies and memory subsystem behavior under server workloads.
• Experience collaborating with verification, validation, performance modeling, and system architects.
• Ability to evaluate third-party IP and make integration recommendations.
• Experience building or using cycle-approximate performance models and interpreting workload-driven results.
• Familiarity with SoC memory hierarchy and system-level memory optimization techniques.
• Must be able to pass Microsoft Cloud Background Check and other required security screenings.

Nice-to-have / preferred:

• Delivered architecture, design, or verification specifications for multiple generations of memory controllers.
• Hands-on familiarity with JEDEC DDR specifications and advanced RDIMM/MRDIMM/LP-MRDIMM variants.
• Experience with HBM, CXL-type memories, or other emerging memory technologies.
• Track record of leading projects end-to-end.

Education Requirements

Posting specifies degree-based equivalencies: Doctorate (PhD) in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 7+ years technical engineering experience; Master’s degree in those fields with 10+ years; Bachelor’s degree in those fields with 12+ years; or equivalent practical experience. Preferred equivalencies increase experience thresholds (e.g., PhD +8, MS +12, BS +15) as noted by the employer.

About the Company

Company: Microsoft

Headquarters: Redmond, Washington, United States

Microsoft is a global technology company that develops and sells software, services, devices, and solutions. Known for its Windows operating system, Office suite, and Azure cloud platform, Microsoft aims to empower individuals and organizations around the world to achieve more. The company fosters a culture of innovation and inclusion, focusing on delivering trusted experiences to customers and partners globally.