Principal Layout Engineer, DPG LPDDR

Job Title

Principal Layout Engineer, DPG LPDDR

Role Summary

Lead physical implementation, full-chip floorplanning, signoff, and tape-out for advanced memory and interface designs within the DPG LPDDR group. You will define and scale layout methodologies, drive automation, and ensure manufacturability and reliability for advanced-node products.

This role leads cross-functional, global teams and mentors engineers to deliver high-quality silicon on schedule.

Experience Level

Senior level — requires extensive industry experience; the posting specifies 15+ years of hands-on custom layout experience.

Responsibilities

Primary responsibilities include ownership of physical implementation and driving execution across teams:

• Lead full-chip floor planning, integration, physical implementation, signoff, and tape-out execution.
• Drive layout implementation for complex analog, mixed-signal, memory, and high-speed interface designs.
• Own closure for DRC, LVS, ERC, EM/IR, reliability, and manufacturability concerns.
• Define and scale layout methodologies, best practices, and execution frameworks.
• Drive automation initiatives using AI/ML and agentic AI to improve layout productivity, quality, and decision-making.
• Lead cross-functional and global teams; mentor engineers and promote technical excellence.

Requirements

Must-have technical skills, experience, and leadership qualifications:

• 15+ years of hands-on custom layout experience and proven success leading full-chip programs from concept through silicon tape-out.
• Deep expertise in analog & mixed-signal layout, memory & high-speed interface layout, and full-chip floor planning and integration.
• Strong knowledge of signal integrity, power integrity, EM/IR, physical verification, and signoff flows.
• Experience with advanced-node technologies (FinFET/GAA).
• Proficiency with Cadence Virtuoso, Calibre, StarRC, Totem, and related EDA tools.
• Strong scripting and automation skills (Python, SKILL, Tcl) and experience building automation for layout tasks.
• Proven technical leadership, communication, and problem-solving abilities; experience leading cross-functional teams.
• Proven experience leveraging AI/Generative AI/Agentic AI to improve engineering productivity and design automation.

Nice-to-have:

• Experience with LPDDR, HBM, NAND, SERDES, PCIe, UCIe, or advanced SoC products.
• Experience building and deploying AI-powered engineering workflows and intelligent design agents.
• Prior work on global tape-out programs and manufacturing ramp.

Education Requirements

B.Tech or M.Tech in Electrical Engineering, Electronics, VLSI, or a related field (as specified in the posting).

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.