Principal Interconnect Design Engineer

Job Title

Principal Interconnect Design Engineer

Role Summary

Principal hardware engineer responsible for architecting and delivering high-performance interconnect and uncore IP (TileLink, cache controllers, protocol bridges) as configurable RTL generators. The role sits on SiFive's CPU and interconnect IP team and focuses on design, integration, and early verification to meet performance, configurability, and time-to-market goals.

Compensation note: base pay range provided in the original posting; see employer materials for final offer details.

Experience Level

Senior-level engineer. Title indicates principal/senior responsibility; relevant experience typically corresponds to senior-level roles (no explicit years of experience specified).

Responsibilities

Design, implement, and integrate configurable interconnect and uncore hardware as generator-based RTL, and collaborate with verification and documentation teams.

• Architect, design, and implement enhanced TileLink interconnects, cache controllers, protocol bridges, and related infrastructure as RTL generators (Chisel-based).
• Implement self-configuring RTL generator elements that correctly interconnect across configurations.
• Drive performance and multi-core/multi-system coherence improvements in future designs.
• Design extensive configurability as a primary design consideration.
• Integrate new IP into the Chisel/FIRRTL framework and contribute improvements that enable automated configuration, documentation, verification testbenches, and software packaging.
• Perform initial sandbox verification and collaborate with the design verification team to create and execute verification plans.
• Create and maintain design documentation and participate in collaborative engineering processes.

Requirements

Must-have technical skills and capabilities for successful execution of the role.

• Deep knowledge of cache architectures and cache coherence concepts.
• Experience with NoC or other interconnect fabrics and ability to architect connections across disparate bus protocols.
• Familiarity with industry-standard bus protocols such as AXI, AHB, APB, CHI, CXL, UCIe.
• Strong software engineering background, including functional programming and software-driven hardware design patterns.
• Experience with templated/metaprogramming and compiler infrastructure for domain-specific languages or IRs.
• Experience writing adaptive unit tests and practicing test-driven development.
• Proficiency with RTL design in Verilog, SystemVerilog, or VHDL.
• Attention to detail, focus on high-quality design, and ability to work effectively in teams.

Nice-to-have

• Experience with Scala/Chisel, Bluespec, or other DSLs for configurable hardware generation.
• Knowledge of RISC-V architecture and ecosystem.
• Experience with Git/GitHub, Jira, and Confluence.

Education Requirements

BS or MS in Electrical Engineering (EE), Computer Engineering (CE), Computer Science (CS), or a related technical discipline, or equivalent practical experience.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.