Principal High-Speed Interface Verification Engineer

Job Title

Principal High-Speed Interface Verification Engineer

Role Summary

Lead a verification team responsible for mixed-signal SerDes IP verification, covering architecture, test plans, mixed-signal co-simulation, and closure of functional and coverage goals. The role spans digital and analog verification, customer escalation handling, and pre-sales technical support.

Experience Level

Senior - requires extensive experience; the posting specifies 15+ years of hands-on verification experience.

Responsibilities

Primary responsibilities include planning, directing, and delivering verification activities for high-speed interface IP across digital and mixed-signal domains.

• Lead and mentor a verification team, set technical direction, and ensure timely delivery and quality.
• Define verification test plans with clear coverage goals and drive coverage closure (functional, code, assertion).
• Modify and extend UVM/VMM SystemVerilog testbenches to support mixed-signal co-simulation with analog models.
• Analyze and verify SerDes functions such as clock-data recovery, equalization, and link training for protocols (PCIe Gen5/6, 400G Ethernet, USB3.1).
• Debug simulation failures spanning analog waveforms and digital logic; collaborate with mixed-signal engineers to isolate root cause and validate fixes.
• Manage customer escalations related to verification quality, silicon bugs, or testbench issues and support pre-sales technical discussions.

Requirements

Core technical skills and leadership experience required to perform the role.

Must-have:

• Extensive experience across the ASIC flow: architecture, digital design, verification, physical implementation, and hardware bring-up.
• Proven experience building and running UVM testbenches, including constrained-random tests, scoreboards, and coverage-driven closure.
• Practical experience with digital/analog co-simulation methodologies and mixed-signal simulation environments (e.g., Cadence AMS Designer, Synopsys VCS AMS, or equivalent).
• Strong understanding of high-speed interface protocols (PCIe Gen3+; Ethernet 10G–400G; USB3.1 or similar SerDes-based standards).
• Proven ability to lead technical teams, manage customer escalations, and communicate complex verification issues to engineering teams and external stakeholders.

Nice-to-have:

• Experience debugging at the boundary between digital logic and analog circuits, including reading SPICE netlists and interpreting analog waveforms.
• Experience reducing simulation time and improving coverage efficiency through methodology improvements.

Education Requirements

MTech or BTech degree specified; position requires 15+ years of hands-on verification experience in ASIC development.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.