Principal High-Speed I/O Architect (PCIe, CXL, UA Link)

Job Title

Principal High-Speed I/O Architect (PCIe, CXL, UA Link)

Role Summary

Design on-chip interconnect architectures (coherent and non-coherent) for scalable SoC platforms across mobile, automotive, datacenter, networking, and IoT markets. Lead architecture and roadmap for high-speed I/O subsystems and work with cross-functional teams to deliver production-quality silicon and system-level solutions.

Engage early with customers, define implementation-ready specifications, and collaborate with software, firmware, performance, power, and physical design teams to optimize end-to-end solutions.

Experience Level

Senior (Principal). Typical candidate has 10+ years in semiconductor architecture or design; the posting also references 8+ years of protocol/coherency experience in relevant areas.

Responsibilities

Core responsibilities include:

• Architect high-speed interconnect subsystems (PCIe, CXL, UA Link) and define coherent/non-coherent communication architectures.
• Define IP and subsystem roadmaps for high-speed I/O and interconnect technologies in partnership with SoC architecture and core technology teams.
• Lead early architecture engagements with customers to shape system requirements and deliver implementation-ready specifications.
• Collaborate with performance, power, and physical design teams to optimize subsystem behavior, bandwidth, latency, and overall system efficiency.
• Develop SoC architecture that integrates Arm IP and high-speed I/O subsystems to meet compute, memory, and interconnect performance targets.
• Partner with software, firmware, and platform teams to optimize hardware, drivers, and system software across the stack.
• Support use-case exploration, workload analysis, and performance modeling to guide architectural decisions.

Requirements

Must-have skills and experience:

• Deep expertise in PCIe, CXL, and UA Link protocols, including link-level behavior, transaction flows, ordering models, memory expansion/pooling, die-to-die/chiplet connectivity, and host/device integration.
• Experience with coherency protocols, hierarchical cache design, and system-level coherency architectures.
• Proven collaboration with performance, power, and physical design teams on the PCIe/CXL/UA Link stack.
• Strong knowledge of heterogeneous compute, subsystem design, security, caching, and memory systems.
• Demonstrated communication and leadership skills with ability to influence executive stakeholders and multi-functional teams.

Nice-to-have:

• Ability to thrive in dynamic environments with shifting priorities.
• Strategic mindset and constructive approach to improving the status quo.
• Track record of delivering complex projects on time and to specification.

Education Requirements

Bachelor's or Master's degree in Electrical or Computer Engineering (or equivalent practical experience). The role expects senior-level experience—typically 10+ years in semiconductor architecture, design, or related roles; equivalent experience may be accepted.

About the Company

Company: Arm

Headquarters: Cambridge, United Kingdom

ARM is a global leader in semiconductor and software design, driving innovation in computing technology. The company specializes in designing processors and systems that provide the essential building blocks for electronic devices. ARM's architecture is widely used in smartphones, servers, and IoT devices, and its collaborative culture fosters bold thinking, diversity, and high-impact benefits for its talented workforce.