Principal High-Speed I/O Architect (PCIe, CXL, UA Link)

Job Title

Principal High-Speed I/O Architect (PCIe, CXL, UA Link)

Role Summary

The Principal High-Speed I/O Architect defines and designs on-chip coherent and non-coherent interconnect architectures and high-speed I/O subsystems for scalable SoC platforms. The role partners with SoC architects, IP teams, performance, power, physical design, firmware and software teams to deliver production-quality silicon across markets such as mobile, automotive, datacenter, networking, and IoT.

Experience Level

Senior — position expects an experienced architect. The posting references 10+ years in semiconductor architecture/design roles and 8+ years working with coherency protocols and system-level coherency architectures.

Responsibilities

Design, specify, and lead high-speed I/O and interconnect architecture work across silicon products and customer engagements.

• Architect PCIe, CXL, and UA Link subsystems and define coherent and non-coherent communication architectures for SoCs.
• Define IP and subsystem roadmaps for high-speed I/O in collaboration with SoC architecture and core-technology teams.
• Lead early architecture engagements with customers to capture system requirements and produce implementation-ready specifications.
• Work with performance, power, and physical design teams to optimize bandwidth, latency, power, and system efficiency.
• Integrate Arm IP and high-speed I/O subsystems into SoC architectures to meet compute, memory, and interconnect targets.
• Partner with software, firmware, and platform teams to optimize end-to-end hardware and system software solutions.
• Perform use-case exploration, workload analysis, and performance modeling to guide architectural decisions.

Requirements

Key technical and interpersonal requirements. Education degree details are summarized separately under Education Requirements.

Must-have

• Deep expertise in PCIe, CXL, and UA Link protocols, including link-level behavior, transaction flows, ordering models, memory expansion/pooling, die-to-die or chiplet connectivity, and host/device integration.
• Experience with coherency protocols, hierarchical cache design, and system-level coherency architectures (posting cites 8+ years for this area).
• Track record collaborating with performance, power, and physical design teams on high-speed I/O stacks.
• Strong knowledge of heterogeneous compute, security, caching, and memory systems.
• Demonstrated communication and leadership skills with the ability to influence executive stakeholders and cross-functional teams.

Nice-to-have

• Experience delivering complex projects to specification and on schedule.
• Ability to adapt to dynamic priorities and contribute constructively to improving existing designs and processes.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering or Computer Engineering (or equivalent). The posting allows "or equivalent" practical experience and references 10+ years of experience in semiconductor architecture, design, or related roles.

About the Company

Company: Arm

Headquarters: Cambridge, United Kingdom

ARM is a global leader in semiconductor and software design, driving innovation in computing technology. The company specializes in designing processors and systems that provide the essential building blocks for electronic devices. ARM's architecture is widely used in smartphones, servers, and IoT devices, and its collaborative culture fosters bold thinking, diversity, and high-impact benefits for its talented workforce.