Principal Hardware Application Engineer

Job Title

Principal Hardware Application Engineer

Role Summary

Hands-on, customer-facing hardware application engineer based in Taiwan supporting Marvell's data-center networking platforms. Works with customer hardware teams and internal cross-functional groups (SI/PI, PSE, software AE) to drive design-in, bring-up, debugging, and production readiness.

Experience Level

Senior — typically requires 8+ years of hardware design or hardware application engineering experience for high-speed networking or data center systems.

Responsibilities

Primary responsibilities include technical account support, schematic/layout review, SI/PI analysis, and board bring-up.

• Serve as the primary hardware technical contact for strategic accounts; lead design-in from schematic review through board bring-up, EDVT, and mass production.
• Review customer PCB schematics and layouts; advise on component selection, power sequencing, clock distribution, and high-speed routing.
• Perform or coordinate signal integrity and power integrity simulations (pre- and post-layout) for high-speed Ethernet interfaces (e.g., 800G, 1.6T).
• Evaluate channel performance, SerDes tuning (Tx EQ / Rx CTLE), and PAM4 link margin.
• Support board bring-up and debug at customer sites and in the Taipei lab for SerDes training, power integrity, thermal, and interface failures.
• Author and review hardware design guides, application notes, schematic checklists, and layout guidelines.
• Collaborate with global EE/ME/SI/PI and silicon/platform teams to represent customer requirements and feed back design insights.
• Investigate next-generation interconnect technologies and contribute to internal training and knowledge sharing.
• Engage Taiwan supply-chain partners (PCB materials, thermal, power components, connectors, cabling) to optimize platform designs.

Requirements

Must-have technical skills and behaviors for the role.

• Minimum 8 years' experience in hardware design or hardware application engineering for high-speed networking or data-center systems.
• Proficiency with schematic capture and PCB layout review tools (e.g., Cadence OrCAD, Mentor PADS, Cadence Allegro, or equivalent).
• Strong knowledge of signal integrity for high-speed differential interfaces: channel loss, eye analysis, SerDes Tx/Rx equalization, and PAM4 link budgets.
• Familiarity with power integrity concepts: PDN design, AC/DC simulation, decoupling strategy, and power sequencing.
• Experience supporting customers through schematic/layout review, bring-up, and EDVT.
• Strong written and verbal communication; able to present technical findings to engineering teams and customers.
• Proactive, self-driven, and able to manage multiple customer engagements in parallel.

Nice-to-have:

• Hands-on experience with DC switch or high-speed Ethernet platforms (e.g., 400G, 800G, 1.6T).
• Familiarity with Marvell Teralynx (TL7, TL10, T100) or equivalent DC switch silicon.
• Experience with SI/PI simulation tools (Sigrity, Ansys SIwave, HFSS, PowerDC) and board bring-up instruments (oscilloscopes, VNAs, BERT, real-time sampling scopes).
• Knowledge of UALink, ESUN, CPO, 224G SerDes, thermal design for high-power switching platforms, and MSDC/ODM requirements.

Education Requirements

Bachelor's degree or above in Electrical Engineering, Electronics Engineering, or a related technical field. No certifications or explicit equivalent-experience language are specified in the posting.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.