Principal Hardware Application Engineer

Job Title

Principal Hardware Application Engineer

Role Summary

Hands-on, customer-facing hardware application engineering role based in Taiwan supporting Marvell's data center networking platforms. Acts as the primary technical contact for strategic accounts, coordinating across Marvell engineering, SI/PI, software, and supplier teams to drive schematic review, board bring-up, EDVT, and production.

This role is eligible to participate in Marvell's bonus and equity plans.

Experience Level

Senior - typically requires 8+ years of relevant experience in hardware design or hardware application engineering for high-speed networking or data center systems.

Responsibilities

Key responsibilities include customer engagement, design review, simulation, and on-site bring-up support.

• Serve as the primary hardware technical focal for strategic customers; lead design-in from schematic review through mass production.
• Review customer PCB schematics and layouts; advise on component selection, power sequencing, clock distribution, and high-speed routing.
• Perform or coordinate SI/PI simulations (pre- and post-layout) for high-speed Ethernet interfaces (e.g., 800G, 1.6T) and recommend SerDes tuning.
• Support board bring-up and debug at customer sites and in the Taipei lab; troubleshoot SerDes link training, power integrity, thermal, and interface issues.
• Author and review hardware design guides, application notes, schematic checklists, and layout guidelines.
• Participate in cross-functional EE/ME/SI/PI design reviews and relay customer requirements to silicon and platform teams.
• Explore and evaluate next-generation interconnect technologies and engage Taiwan supply-chain partners to optimize platform designs.

Requirements

Must-have:

• 8+ years experience in hardware design or hardware application engineering for high-speed networking or data center systems.
• Proficiency with schematic capture and PCB layout review tools (e.g., Cadence OrCAD, Mentor PADS, Cadence Allegro or equivalent).
• Solid knowledge of signal integrity for high-speed differential interfaces: channel loss, eye analysis, SerDes Tx/Rx equalization, and PAM4 link budgets.
• Familiarity with power integrity: PDN design, AC/DC simulation, decoupling strategies, and power sequencing.
• Experience supporting customers through schematic/layout review, board bring-up, and EDVT.
• Strong communication skills and the ability to manage multiple customer engagements concurrently.

Nice-to-have:

• Hands-on experience with DC switch or high-speed Ethernet platforms (400G, 800G, 1.6T).
• Familiarity with Marvell Teralynx (TL7, TL10, T100) or equivalent DC switch silicon.
• Experience with SI/PI simulation tools (Sigrity, Ansys SIwave, HFSS, PowerDC, etc.).
• Knowledge of next-generation interconnects (UALink, ESUN, CPO, 224G SerDes) and thermal design for high-power switches.
• Familiarity with MSDC ODM requirements, Taiwan supply-chain ecosystem, and board bring-up tools (oscilloscopes, VNAs, BERTs, sampling scopes).

Education Requirements

Bachelor's degree or above in Electrical Engineering, Electronics Engineering, or a related technical field.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.