Principal Foundry Interface Design Engineer, HBM

Job Title

Principal Foundry Interface Design Engineer, HBM

Role Summary

Member of the HBM Design Architecture team supporting design, technology, and manufacturing for advanced HBM DRAM products. Serves as the technical bridge between internal design teams, foundries, and technology development groups to translate process capabilities into scalable, high-performance memory architectures.

Work focuses on foundry interface, circuit simulation and analysis, test-chip validation, PDK/design enablement, and AI-enabled productivity improvements that affect performance, power, reliability, and roadmap decisions.

Experience Level

Senior - requires substantial industry experience (see Requirements). The posting specifies 6+ years of semiconductor industry experience.

Responsibilities

Primary responsibilities span technology alignment with foundries, circuit and layout analysis, silicon validation, PDK and design enablement, and automation using AI where appropriate.

• Act as the principal technical interface with foundry partners; close design-process gaps and influence foundry roadmaps (TSV, BEOL, reliability, design enablement).
• Define technology requirements for future HBM and custom memory products.
• Perform HSPICE simulations, evaluate compact/PDK SPICE models, and run pre-layout and post-layout circuit analyses.
• Support BEOL optimization and routing studies; develop methodologies to evaluate sensitivity to process variations.
• Plan and implement technology evaluation test chips; define process monitor structures and benchmark vehicles; analyze post-silicon data and correlate with simulation.
• Evaluate foundry PDKs and IP collateral; create design recommendations, analog guidelines, and digital PPA evaluation methods; collaborate with CAD teams on flow enablement and validation.
• Identify and implement AI-enabled workflows and automation to improve DTCO, PDK evaluation, benchmarking, and cross-team collaboration.

Requirements

Must-have technical skills, practical experience, and demonstrated impact.

• 6+ years of semiconductor industry experience with strong understanding of advanced semiconductor technology development.
• Deep knowledge of advanced CMOS technology nodes, FinFET devices, and process integration.
• Hands-on experience with HSPICE simulations, device characterization, standard cell benchmarking, PPA analysis, parasitic extraction, and physical verification.
• Experience implementing AI-enabled engineering practices and automation for DTCO, PDK evaluation, benchmarking, and collaboration.
• Proven experience in at least three of these focus areas: foundry interface, circuit simulation/analysis, test-chip/silicon validation, PDK/design enablement, AI-enabled productivity.

Nice-to-have:

• Experience working directly with leading foundries (TSMC, Samsung, Intel Foundry Services, GlobalFoundries).
• Experience with memory products (DRAM, HBM, SRAM) and advanced packaging/TSV technologies.
• Familiarity with reliability modeling, aging simulations, advanced BEOL technologies, and PDK development/validation.
• Experience leading technology pathfinding, node selection activities, and applying AI tools to analyze PDKs, DRMs, reliability reports, and silicon characterization data.

Education Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience. (This posting explicitly allows degree or equivalent experience.)

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.