Principal Firmware/Middleware Architect

Job Title

Principal Firmware/Middleware Architect

Role Summary

The Principal Firmware/Middleware Architect will define, design, and drive the end-to-end embedded software and firmware architecture for next-generation AI cluster scale-up switches (UALink family). The role bridges ASIC/RTL teams and higher-level orchestration software to ensure deterministic performance, reliability, and secure operation across large-scale AI fabrics.

Experience Level

Senior-level. The posting specifies 15+ years of hands-on experience in embedded systems, server platform architecture, or low-level silicon firmware development.

Responsibilities

Lead firmware architecture and implementation for scale-up switch ASICs, from low-level MCU firmware to APIs exposed to platform controllers.

• Architect low-level firmware for internal microcontrollers on UALink switch ASICs and specify interfaces, registers, and memory maps.
• Collaborate with ASIC, RTL, and verification teams on hardware–software co-design and integration.
• Define and implement firmware stacks for physical, link, and transport layers including credits, routing tables, and flow control.
• Design deterministic link initialization and fast link-training state machines for die-to-die and chassis-to-chassis links.
• Architect runtime topology discovery, dynamic routing, and credit management to avoid fabric congestion.
• Lead design of SDKs/APIs to expose switch functionality to BMCs and orchestration software (e.g., OpenBMC/Redfish).
• Optimize bare-metal execution paths for deterministic low-latency collective communications (All-Reduce, All-to-All).
• Specify and implement RAS mechanisms: telemetry, error handling, fault isolation, fallback modes, and FEC strategies.
• Design and enforce security primitives: secure boot, cryptographic firmware authentication, and runtime attestation.

Requirements

Core technical and professional requirements for immediate contribution.

• Must-have: 15+ years' experience in embedded systems, server platforms, or low-level silicon firmware.
• Must-have: Expert-level C for bare-metal/RTOS environments; proficient in Python for automation and modeling.
• Must-have: Deep knowledge of high-speed interconnects and protocols (examples noted: UALink, NVLink, CXL, PCIe Gen5/Gen6).
• Must-have: Strong understanding of switching concepts: credit-based flow control, routing, PHY equalization, and SerDes management.
• Must-have: Hands-on experience with hardware debuggers (JTAG, TRACE32) and lab instrumentation (oscilloscopes, protocol analyzers).
• Must-have: Proven ability to collaborate with ASIC/RTL/verification teams and define HW–SW interfaces.
• Nice-to-have: Experience with RTOS options (ThreadX, FreeRTOS, Zephyr), OpenBMC/Redfish integration, advanced RAS micro-architectures, and secure-boot/attestation implementations.

Education Requirements

Bachelor's, Master's, or Ph.D. in Computer Engineering, Electrical Engineering, Computer Science, or a related discipline.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.