Principal Ethernet Scale-Out Architect, AI Data Center

Job Title

Principal Ethernet Scale-Out Architect, AI Data Center

Role Summary

Architect large-scale Ethernet-based fabrics and interconnects for AI datacenter products, spanning accelerator cards, servers, racks, and multi-rack clusters. Partner with SoC, software, card, platform, and product teams to define system architecture, requirements, and performance tradeoffs for data movement, telemetry, security, and reliability.

Experience Level

Senior. Typical background: 8+ years relevant experience (see Education Requirements for degree-based experience equivalencies).

Responsibilities

Key responsibilities include designing and validating system-level networking and data-movement architectures for AI datacenters.

• Define next-generation scale-out network architectures for AI and cloud datacenters.
• Develop end-to-end system architecture spanning accelerator cards, servers, racks, and multi-rack clusters.
• Drive architecture and requirements for Ethernet fabrics, NICs/SuperNICs, switch ASICs, transport protocols, in-network collectives, telemetry, security, virtualization, RAS, and reliability.
• Analyze DMA engines, data flows, packet flows, and system bottlenecks to optimize bandwidth, latency, utilization, and scalability.
• Collaborate with software, SoC, card, platform, and validation teams to implement connectivity solutions for scale-up and scale-out deployments.
• Provide technical leadership across physical, link, transaction, transport, and protocol layers of high-speed interfaces and datacenter networking systems.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• 8+ years of hardware architecture, design, validation, testing, or commercialization experience in datacenter, networking, accelerator, or high-speed I/O products.
• Strong understanding of Ethernet, InfiniBand, RoCEv2, RDMA, and related transport protocols.
• Experience working with software teams to optimize end-to-end data movement for high bandwidth and low latency.
• 3+ years working with datacenter products such as servers, accelerators, NICs, switches, racks, or cluster-scale systems.
• In-depth knowledge of high-speed SerDes, PCIe/CXL-class interfaces, and board/system-level connectivity tradeoffs.
• Expertise in telemetry, observability, RAS, reliability, error handling, and failure-mode analysis at scale.
• Understanding of security, isolation, virtualization, and multi-tenant deployment requirements.
• Knowledge of DMA engines, memory hierarchy, I/O virtualization, and accelerator data-movement architectures.
• Ability to operate effectively in cross-functional, international, multi-site engineering environments.

Education Requirements

Bachelor's degree in Science, Engineering, or related field plus 8+ years of relevant ASIC design/verification/validation/integration experience; OR Master's degree plus 7+ years; OR PhD plus 6+ years. Equivalency by relevant practical experience is acceptable per listing. Fields referenced: science and engineering disciplines or related technical fields.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.