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Principal ESD Engineer

Renesas
September 16, 2026
Full-time
On-site
Chandler, Arizona, United States
Device Engineering Jobs, Level - Senior

Job Title

Principal ESD Engineer

Role Summary

Lead development of ESD architecture, protection IP, and sign-off verification for advanced-node semiconductor products, including FinFET technologies and high-speed interfaces. Work with chip design teams, foundries, and EDA vendors to define ESD strategies and ensure silicon-level robustness.

Primary location: Chandler, AZ; additional consideration for Palm Bay, FL.

Experience Level

Senior - 10+ years of semiconductor ESD design experience.

Responsibilities

Responsible for technical leadership of ESD methodology, IP, and verification across product families.

  • Define and lead ESD architecture and sign-off strategy for advanced-node products.
  • Design and optimize custom ESD protection devices, clamps, and IP.
  • Provide co-design guidance to balance performance and protection.
  • Develop and maintain automated ESD verification methodologies and flows.
  • Lead sign-off reviews and risk assessments for complex SoCs and mixed-signal designs.
  • Support silicon characterization (HBM, CDM, TLP, VF-TLP) and Latch-Up testing.
  • Perform root-cause analysis of ESD failures and drive corrective actions.
  • Collaborate with foundries, EDA vendors, and global design teams.

Requirements

Must-have technical skills and experience:

  • 10+ years ESD design experience in semiconductors, including FinFET technologies.
  • Deep knowledge of ESD device physics and protection mechanisms (HBM, CDM, TLP, VF-TLP, Latch-Up).
  • Hands-on experience with ESD cell design and custom ESD IP for SoCs and SerDes.
  • Proven experience with ESD sign-off methodologies and verification techniques.
  • Experience with Calibre PERC or equivalent ESD verification tools.
  • Experience supporting silicon characterization and test methods.
  • Demonstrated leadership in cross-functional engineering programs.
  • Strong technical writing and global communication skills.

Nice-to-have:

  • Experience developing and maintaining Calibre PERC rule decks.
  • Background supporting AI/HPC/networking/memory/data-center products.
  • Knowledge of IEC/EMC or system-level ESD considerations.

Education Requirements

M.S. or Ph.D. in Electrical Engineering or a related field.


About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.

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Date Posted: 2026-09-01