Principal Engineer - Standard Cell Design

Job Title

Principal Engineer - Standard Cell Design

Role Summary

Lead the architecture and circuit design of standard cell libraries to deliver competitive power, performance, area (PPA) and Vmin across advanced process nodes. Work with DTCO, foundry technology teams, EDA partners and product design teams to define library strategy, validate silicon, and enable scalable library ecosystems for CPU, GPU and SoC products.

Experience Level

Senior level — typically requires 10+ years of industry experience in foundation IP design, design-technology co-optimization, or advanced semiconductor technology.

Responsibilities

Primary responsibilities focus on technical leadership, library architecture, and delivery of high-performance, low-voltage cell solutions.

• Define standard cell library strategy, content, naming, modeling and validation approaches.
• Drive transistor-level circuit innovation for high-performance and low-voltage sequential and clocking circuits.
• Lead PPA and Vmin optimization across process nodes and product lines; balance tradeoffs across performance, power and area.
• Partner with process, DTCO, product design teams and EDA vendors to align scalable solutions and tooling feedback loops.
• Analyze silicon and design data to identify outliers, debug issues and drive improvements.
• Interface with foundry customers and internal stakeholders to identify gaps and co-optimize libraries and process requirements.
• Mentor and develop circuit designers; lead working groups to achieve technical alignment.

Requirements

Must-have technical expertise and professional skills.

• Deep understanding of MOSFET device characteristics, layout effects and variability at advanced nodes.
• Experience with transistor-level design of static circuits and state-retaining elements (latches, flops) and standard cell development.
• Knowledge of PPA tradeoffs, Vmin behavior and variation impacts.
• Experience using standard cell characterization tools and SPICE circuit simulation for cell design and verification.
• Track record of identifying, designing and verifying cells that improve product-level PPA.
• Expertise in low-power and high-performance circuit techniques, especially clocking and sequential elements.
• Ability to analyze data, identify trends, make decisions with incomplete data, and communicate conclusions clearly.
• Collaborative mindset, strong communication skills, and experience mentoring or developing engineers.
• Willingness and ability to undergo and pass an extended background investigation for a Position of Trust.

Education Requirements

Minimum: Ph.D. or Master’s degree. The role also specifies 10+ years of industry experience in foundation IP design, design-technology co-optimization or advanced semiconductor technology.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.