Principal Engineer - Standard Cell Design

Job Title

Principal Engineer - Standard Cell Design

Role Summary

Principal engineer responsible for strategy, architecture, and circuit-level innovation for standard cell libraries used across Intel CPU, GPU, and SoC products. The role leads library content definition, PPA and Vmin optimization, and cross-team co-optimization with process and EDA partners.

Works with DTCO, product design teams, foundry customers, and EDA partners to ensure scalable, high-performance library solutions and mentors other engineers.

Experience Level

Senior (Principal) — requires significant experience; posting indicates 10+ years of industry experience.

Responsibilities

Core responsibilities include driving library strategy, circuit innovation, and cross-functional alignment. Key activities:

• Define standard cell library strategy: content, cell selection, naming, modeling, and validation frameworks.
• Design and optimize circuits for high-performance and low-voltage operation, with emphasis on sequential and clocking elements.
• Lead PPA and Vmin optimization efforts across process nodes and product lines.
• Collaborate with foundry technology teams and EDA partners to co-optimize process and library requirements.
• Interface with internal and external customers to identify library gaps and drive corrective actions.
• Analyze silicon and design data to debug issues, identify trends, and recommend improvements.
• Develop and refine circuit design methodology, best practices, and validation approaches.
• Lead or participate in cross-organizational working groups to achieve technical convergence.
• Mentor and develop junior and mid-level circuit designers and technical leaders.

Requirements

Must-have technical skills and attributes; preferred items listed when available.

• Deep knowledge of MOSFET electrical behavior, device physics, layout impacts, and variability at advanced nodes.
• Experience with transistor-level design of static circuits, including latches and flip-flops, and standard cell development.
• Understanding of standard cell tradeoffs across power, performance, area, and Vmin.
• Experience with standard cell characterization tools and SPICE circuit simulation flows.
• Track record of identifying, designing, and verifying cells that improve product-level PPA.
• Expertise in low-power, high-performance circuit techniques, including clocking and sequential elements.
• Strong data analysis skills; ability to identify trends and communicate conclusions clearly.
• Proven ability to lead technically, collaborate across teams, and mentor junior engineers.
• Excellent oral and written communication and strong problem-solving skills in ambiguous, complex environments.
• Nice-to-have: background in compact modeling, characterization, EDA tool interaction, block-level feedback tools, publications or patents, and prior experience with CPU/GPU/SoC teams.

Education Requirements

Minimum: Ph.D. or Master’s degree (posting specifies these degrees). The posting also specifies 10+ years of industry experience. No specific fields of study were listed.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.