Principal Engineer, SoC PnP Architect

Job Title

Principal Engineer, SoC PnP Architect

Role Summary

Lead SoC performance, power and PnP (power, noise, and performance) architecture work across pre-silicon, emulation, and post-silicon phases. Work with architecture, design, firmware, software and validation teams to identify system-level bottlenecks and drive measurable improvements in performance, power, and efficiency.

Experience Level

Senior-level. The role expects extensive domain experience; the posting specifies 15+ years in SoC PnP architecture within the semiconductor industry.

Responsibilities

Primary responsibilities include technical leadership of system-level performance and power investigations and delivering actionable architecture guidance.

• Lead system-level performance and power analysis across compute, interconnect, memory, and IO subsystems.
• Perform pre-silicon performance analysis using cycle-accurate, transaction-level, and emulation environments; use platforms such as Palladium, Veloce, ZeBu or equivalents.
• Develop, calibrate and maintain performance and power models (SystemC/TLM, analytical, trace-driven) and correlate model outputs with emulation and silicon measurements.
• Support silicon bring-up and post-silicon performance/power characterization, including counter/PMU/telemetry-driven investigations and root-cause analysis.
• Identify system bottlenecks (latency, bandwidth, QoS, utilization) and propose architecture, IP configuration, memory/interconnect sizing, or QoS strategies.
• Perform waveform and signal-level analysis, transaction-level tracing and protocol debug across CHI/AXI/PCIe/CXL or equivalent protocols.
• Develop tooling, automation and data pipelines for profiling, telemetry correlation, and visualization.
• Present findings and recommendations to cross-functional stakeholders and influence product-level decisions.
• Lead multi-team investigations and convert debug outcomes into tuning proposals or architectural improvements.

Requirements

Must-have skills and experience required for the role.

• 15+ years of SoC PnP architecture experience in the semiconductor industry.
• Proven expertise in SoC performance architecture, pre-silicon performance analysis, and model-to-silicon correlation.
• Hands-on experience with emulation/simulation platforms (Palladium, Veloce, ZeBu or equivalent) and cycle-accurate or transaction-level analysis.
• Experience developing and calibrating SystemC/TLM, analytical or trace-driven performance and power models.
• Post-silicon bring-up and characterization experience using PMU, telemetry and trace-based methods.
• Strong knowledge of coherent interconnects, cache-coherency, DDR memory subsystems, IO (PCIe, CXL), DVFS and power management mechanisms.
• Proficiency in C/C++ and Python for tool development, automation and data analysis.
• Excellent communication and cross-functional collaboration skills; ability to present complex technical findings to leadership and engineering teams.

Nice-to-have:

• Experience with waveform-based debug, protocol tracing across CHI/AXI/PCIe/CXL, and workload-level tuning under thermal/voltage/Frequency/TDP constraints.
• Background in CPU/GPU/NPU/DSP microarchitecture and workload characterization.

Education Requirements

Not specified.

About the Company

Company: Arm

Headquarters: Cambridge, United Kingdom

ARM is a global leader in semiconductor and software design, driving innovation in computing technology. The company specializes in designing processors and systems that provide the essential building blocks for electronic devices. ARM's architecture is widely used in smartphones, servers, and IoT devices, and its collaborative culture fosters bold thinking, diversity, and high-impact benefits for its talented workforce.