Principal Engineer, SoC Engineering

Job Title

Principal Engineer, SoC Engineering

Role Summary

Lead multi-disciplinary ASIC/FPGA design teams within the Synopsys Solutions group to deliver turnkey SoC designs from requirements through GDSII handoff. The role balances hands-on RTL and architecture work with technical leadership, customer engagement, and cross-functional coordination (verification, DFT, physical design).

Experience Level

Senior - principal-level engineering role. Requires extensive senior experience; posting specifies 15+ years of hands-on ASIC/FPGA design and delivery.

Responsibilities

Primary responsibilities include technical leadership, architecture, and delivery of complex SoC designs:

• Lead teams through full ASIC/FPGA development cycles from specification to GDSII handoff.
• Partition and architect SoC designs from customer requirements into high-level and micro-architectures balancing performance, area, and power.
• Drive RTL development and quality using SystemVerilog, code reviews, lint, CDC/RDC analysis, and synthesis readiness checks.
• Collaborate with verification, DFT, and physical design to resolve integration, timing closure, and DFT issues.
• Implement and integrate industry-standard protocols (PCIe, Ethernet, UCIe) in production designs.
• Develop and refine ASIC design flows and methodologies using Synopsys and vendor EDA tools.
• Work directly with customers across markets (HPC, automotive, aerospace, defense) to translate requirements into implementable architectures.

Requirements

Must-have technical and leadership qualifications. Degree requirements are listed separately under Education Requirements.

• 15+ years of hands-on experience designing and verifying ASIC or FPGA devices with multiple tape-outs or production releases.
• Proven track record of leading design teams and managing technical execution across project milestones.
• Deep knowledge of the full ASIC design flow: micro-architecture, RTL development, synthesis, timing closure, and physical design handoff.
• Strong SystemVerilog RTL coding and review skills for complex control and datapath logic.
• Experience with ASIC development tools: simulators, lint tools, CDC/RDC checkers, synthesis tools, and static timing analysis.
• Practical experience implementing protocols such as PCIe, Ethernet, or UCIe in production designs.
• Customer-facing experience translating requirements into architectures and defending technical tradeoffs.
• Nice-to-have: domain experience in high-performance computing, automotive, aerospace, or defense; familiarity with Synopsys toolset and IP portfolio.

Education Requirements

Bachelor's degree in Electrical Engineering or Computer Engineering (as stated in the posting).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.