Principal Engineer, SoC DFT

Job Title

Principal Engineer, SoC DFT

Role Summary

Hands-on DFT lead responsible for DFT architecture, implementation, integration, and verification for complex SoCs and subsystems from specification through tapeout. This is a customer-facing technical role within the Systems Solutions Group focused on delivering production-ready test solutions and driving cross-functional closure on testability risks.

Experience Level

Senior — typically 10+ years of hands-on SoC DFT experience.

Responsibilities

Primary responsibilities include technical ownership of DFT across design and delivery phases and collaboration with internal and customer teams.

• Own DFT architecture, implementation, integration, and verification for complex SoCs/subsystems from spec through tapeout.
• Define and execute test strategies across scan/ATPG, memory BIST, logic BIST, and analog/PHY test considerations to meet coverage, yield, and cost targets.
• Identify testability risks early, propose design changes, and drive closure across the RTL-to-GDS flow to achieve DFT signoff readiness.
• Develop and institutionalize reusable DFT methodologies, checklists, and guidelines using Synopsys EDA tools.
• Partner with silicon validation and test engineering on post-silicon debug, failure analysis triage, and pattern refinement.
• Collaborate with RTL design, functional verification, physical design, timing, and power teams to ensure testability is designed-in.
• Provide technical guidance through design reviews and integration/debug support (no formal people management required).

Requirements

Must-have technical skills and experience; items noted as preferred are not mandatory.

• Typically 10+ years of hands-on SoC DFT experience with depth in scan/ATPG, memory BIST, and logic BIST.
• Proven track record owning DFT implementation for complex SoCs that have taped out and gone into production.
• Strong understanding of the end-to-end SoC design flow: microarchitecture → RTL → verification → synthesis → timing/physical implementation → signoff.
• Working knowledge of Synopsys DFT tools such as TetraMAX, DFT Compiler, and BIST Architect (preferred).
• Experience driving cross-functional technical decisions and communicating tradeoffs in schedule, cost, and yield.
• Post-silicon debug and collaboration with test engineering to refine production test programs (preferred).

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or a related field.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.