Principal Engineer, SoC Design

Job Title

Principal Engineer, SoC Design

Role Summary

Senior SoC architect and RTL lead responsible for defining SoC and microarchitecture for advanced memory subsystem solutions within Samsung's DRAM Development Lab (DDL).

The role owns SystemVerilog/Verilog RTL design and SoC integration, collaborates with firmware and verification teams, and supports pre-silicon validation and post-silicon bring-up.

Experience Level

Senior — typically 15+ years of SoC architecture and RTL development experience preferred.

Responsibilities

Deliver hands-on RTL implementations and drive SoC-level design decisions for memory and storage solutions.

• Define SoC architecture and microarchitecture for advanced memory subsystems.
• Own RTL design and implementation using SystemVerilog/Verilog.
• Design SoC integration including memory subsystems, high-speed interfaces, clocking, reset, power, and configuration infrastructure.
• Collaborate with architecture, firmware, verification, and system teams to deliver designs.
• Support verification by debugging simulation, emulation, and formal results; resolve functional, performance, and connectivity issues.
• Support pre-silicon validation and post-silicon bring-up through root-cause analysis and debugging.
• Optimize system performance, power, area, and timing through architectural tradeoff analysis.
• Produce design documentation, block specifications, and participate in design reviews.

Requirements

Core technical and leadership requirements for the role. Education details are in the Education Requirements section below.

• Must-have: Deep understanding of modern DRAM technologies: architecture, timing, protocols, training, and controller/PHY interactions.
• Must-have: Experience designing complex SoCs with memory subsystems and high-speed interfaces; strong RTL implementation and timing closure skills.
• Must-have: Proven experience supporting verification and debugging simulation/emulation issues and working with verification teams.
• Must-have: Strong technical leadership, communication, and problem-solving skills; ability to lead cross-functional teams.
• Nice-to-have: FPGA prototyping experience and silicon bring-up experience.
• Nice-to-have: Experience optimizing system-level tradeoffs for performance, latency, bandwidth, power, area, and timing.
• Collaborative mindset and adaptability to global development environments.

Education Requirements

BS in Computer or Electrical Engineering or Computer Science required; MS or PhD preferred. The posting specifies these degree fields explicitly (Computer/Electrical Engineering or Computer Science) and indicates senior-level experience expectations.

About the Company

Company: Samsung Semiconductor

Headquarters: San Diego, California, United States

Samsung Semiconductor is a global leader in semiconductor technology, providing innovative solutions for diverse applications including smartphones, electric vehicles, and data centers. As part of Samsung's Advanced Institute of Technology, the company focuses on cutting-edge research in areas such as CPU microarchitecture, AI, and HPC, fostering a diverse and inclusive work environment for its employees to thrive and innovate.