Principal Engineer, RTL Design

Job Title

Principal Engineer, RTL Design

Role Summary

Lead RTL integration and top-level SoC architecture for complex, multi-block systems including CPUs, GPUs, NPUs, memory subsystems and high-speed peripherals. Drive RTL integration, IP assembly, and cross-functional design closure from microarchitecture to system signoff.

This role provides technical leadership to RTL and integration engineers and collaborates with architecture, verification, physical design, DFT, firmware and software teams.

Experience Level

Senior — requires 12+ years of RTL design and integration experience.

Responsibilities

Deliver architecture and RTL integration for high-performance SoCs and lead cross-discipline implementation activities.

• Define scalable SoC/subsystem partitioning and drive top-level RTL integration and IP assembly.
• Architect and optimize NoC/interconnect for bandwidth, latency, QoS and coherency.
• Integrate high-speed interfaces and ensure protocol compliance (PCIe, DDR/LPDDR, CXL, UCIe, Ethernet, SerDes).
• Integrate heterogeneous compute subsystems (CPUs, GPUs, NPUs, accelerators) and optimize memory hierarchy and coherency.
• Specify and implement clocking, reset, CDC/RDC strategies and support timing-closure activities.
• Lead low-power architecture and UPF-based power intent for multi-voltage, multi-domain designs.
• Define hardware safety and security mechanisms (fault detection/isolation, secure boot, key management).
• Mentor engineers, run architecture/design reviews, and establish RTL quality and signoff practices.

Requirements

Core technical skills and proven leadership in SoC RTL design and integration.

Must-have

• Extensive Verilog/SystemVerilog RTL design and microarchitecture experience.
• Deep understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains and memory subsystems.
• Experience with EDA tools for synthesis, lint, CDC/RDC analysis and timing analysis.
• Familiarity with UPF/low-power design methodologies and power-aware RTL integration.
• Knowledge of formal verification techniques and static/dynamic checks.
• Strong leadership, communication and project management skills; experience with global cross-functional teams.

Nice-to-have

• Experience with NoC architecture, advanced interconnect optimization and QoS tuning.
• Hands-on experience integrating UCIe, PCIe, CXL, high-speed SerDes, DDR/LPDDR or Ethernet subsystems.
• Experience implementing Functional Safety (ISO 26262) and hardware security architectures.

Education Requirements

M.Tech or B.Tech in Electrical Engineering or Computer Science.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.