Principal Engineer — RISC-V CPU Sub-System Architecture

Job Title

Principal Engineer — RISC-V CPU Sub-System Architecture

Role Summary

Lead the architecture and integration of RISC-V CPU sub-systems for modem, connectivity, and embedded control-plane products. The role covers architecture definition, system integration, and silicon execution, collaborating with CPU RTL, SoC, firmware, modeling, and verification teams.

Experience Level

Senior-level role. The posting indicates senior/principal responsibility and typically expects 10+ years of relevant experience.

Responsibilities

Primary accountabilities include system architecture, cross-functional integration, and technical leadership.

• Own CPU sub-system architecture: core integration, cache hierarchy, memory subsystem, and interconnect.
• Define architecture specifications, integration guidelines, and bus/coherency protocols (e.g., AXI, CHI).
• Lead integration of CPU sub-systems into complex SoCs and align HW/SW/firmware teams.
• Define and integrate NoC architecture, including traffic, QoS, and scalability considerations.
• Drive PPA tradeoffs (performance, power, area) and system-level optimization.
• Diagnose system-level issues across architecture, RTL, DV, and firmware; support bring-up and field issue resolution.
• Lead architecture and design reviews and act as technical focal point across global teams.
• Mentor and provide technical guidance to architecture and VLSI engineering teams.
• Own system verification, performance validation, and contribute to product roadmaps and strategic direction.

Requirements

Must-have technical skills and experience. Preferred items listed as nice-to-have.

• Must-have: 10+ years of relevant experience with CPU/SoC architecture and system integration.
• Must-have: Deep knowledge of caches, memory systems, and on-chip interconnects.
• Must-have: Experience with RISC-V or similar ISAs and strong RTL development experience.
• Must-have: Experience with NoC architecture and high-performance bus protocols (AXI, CHI).
• Must-have: Strong problem-solving, system debugging, and communication skills across HW/SW boundaries.
• Nice-to-have: Ownership through full silicon lifecycle, multi-core system design, DDR and modem-specific experience.
• Nice-to-have: Familiarity with firmware–hardware interaction, programming (C/C++, Python), and experience in global matrixed organizations.
• Nice-to-have: Prior technical leadership experience and exposure to project financials or operating budgets.

Education Requirements

Minimum: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field (posting also lists alternate minimums: Bachelor's + 8+ years, Master’s + 7+ years, or PhD + 6+ years). Preferred: Master’s or PhD. The posting also accepts equivalent practical experience in lieu of degrees.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.